|
|
Verilog-A Model Library
|
|
Basic Models
|
 |
Resistors (models, test, dg-vams3-1, dg-vams3-2)
|
|
Capacitors (models, test, dg-vams3-3)
|
|
Inductors (models, test, dg-vams3-4)
|
|
Independent voltage and current sources (models, test, dg-vams3-5, dg-vams3-6)
|
|
Controlled sources (dg-vams3-13)
|
|
Ideal opamp (model, test, dg-vams5-1)
|
|
RLC (dg-vams3-14, dg-vams3-15)
|
|
Resistive port source (dg-vams3-16)
|
|
Relays (controlled switches) (dg-vams3-17, dg-vams3-18, dg-vams3-19)
|
|
Ideal diode (dg-vams3-21)
|
|
|
|
|
|
Functional Models
|
|
Simple logic gates (models, test) |
|
Supply sensitive logic gates (models, test) |
|
D-type flip flop (model, test, dg-vams5-3)
|
|
Data converter (LRM compliant, Spectre compliant, test, dg-vams3-26, dg-vams3-27)
|
|
N-level triggered quantizer (like an ADC followed by a DAC) (model, test, dg-vamsA-1)
|
|
Phase-frequency detectors with charge pump (with and without jitter) (models, test)
|
|
Frequency dividers (with and without jitter) (models, test)
|
|
Fixed-frequency oscillators (with and without jitter) (models, test)
|
|
Voltage controlled oscillators (with and without jitter) (models, test, dg-vams3-22)
|
|
Ideal sample and holds (models, test, dg-vams3-23, dg-vams3-24)
|
|
Current limited voltage regulator (model, test) |
|
Random bit stream generators (models, test, dg-vams5-2)
|
|
Time interval measurement (dg-vams3-25)
|
|
Period measurement (package) |
|
Warn on breakdown (dg-vams5-4)
|
|
Comparator (dg-vams5-5)
|
|
Periodic sampler (LRM compliant, Spectre compliant, test)
|
|
AM, PM, and FM modulators (model, test) |
|
|
|
|
|
Semiconductor Models
|
|
MOS 11 by Geoffrey Coram (model, test)
|
|
Junction diode by Marek Mierzwinski (model, test)
|
|
Simplified junction diodes (dg-vams3-11, dg-vams3-12)
|
|
JFET by Geoffrey Coram (model, test)
|
|
Varistor by Geoffrey Coram (model, test)
|
|
Varactor (model, test, documentation)
|
|
FBH HBT by Matthias Rudolph (vers. 2.1) (model, listing, documentation, package)
|
|
|
|
| Off-Site Models – Original Model Source |
|
|
|
|
|
|
|
|
Verilog-AMS Model Library
|
|
|
|
|
|
Disclaimer
|
Permission to make copies of these models for personal or classroom use is granted without fee provided that the copies are not made or distributed for profit or commercial advantage. To distribute otherwise, to publish, to post on servers, or to distribute to lists, requires prior written permission of the author.
These models are offered as is without warranty. By downloading these files, you agree not to hold either the authors or distributors of the models liable for consequential or incidental damages of any nature whatsoever that results from the use of these models.
Submit models for the Verilog-A/MS model libraries or requests for models by sending them to submit@designers-guide.org.
Extract models from .tgz files using "tar -zxvf filename.tgz".
|
|
|
|
|
|
