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Verilog-A/MS

Reference Material

Verilog-AMS Language Reference Manual

Version 2.3.1 (June 2009) Full (3.7M)
Version 2.3 (August 2008) Full (3.7M), Abridged (2.9M)

Version 2.2 (Nov 2004) Abridged (1.4 MB)

Version 2.1 (Jan 2003) Abridged (1.3 MB)

Full Verilog-AMS LRM is available for a fee from www.accellera.com.

Original Paramset Proposal (200K)

Other Resources

Discussion forum for Verilog-AMS

The Designer's Guide to Verilog-AMS

Learn Verilog-HDL online

Verilog-A Model Library

Basic Models

Resistors (models, test, dg-vams3-1, dg-vams3-2)

Capacitors (models, test, dg-vams3-3)

Inductors (models, test, dg-vams3-4)

Independent voltage and current sources (models, test, dg-vams3-5, dg-vams3-6)

Controlled sources (dg-vams3-13)

Ideal opamp (model, test, dg-vams5-1)

RLC (dg-vams3-14, dg-vams3-15)

Resistive port source (dg-vams3-16)

Relays (controlled switches) (dg-vams3-17, dg-vams3-18, dg-vams3-19)

Ideal diode (dg-vams3-21)

Functional Models

Simple logic gates (models, test)
Supply sensitive logic gates (models, test)

D-type flip flop (model, test, dg-vams5-3)

Data converter (LRM compliant, Spectre compliant, test, dg-vams3-26, dg-vams3-27)

N-level triggered quantizer (like an ADC followed by a DAC) (model, test, dg-vamsA-1)

Phase-frequency detectors with charge pump (with and without jitter) (models, test)

Frequency dividers (with and without jitter) (models, test)

Fixed-frequency oscillators (with and without jitter) (models, test)

Voltage controlled oscillators (with and without jitter) (models, test, dg-vams3-22)

Ideal sample and holds (models, test, dg-vams3-23, dg-vams3-24)

Current limited voltage regulator (model, test)

Random bit stream generators (models, test, dg-vams5-2)

Time interval measurement (dg-vams3-25)

Period measurement (package)

Warn on breakdown (dg-vams5-4)

Comparator (dg-vams5-5)

Periodic sampler (LRM compliant, Spectre compliant, test)

AM, PM, and FM modulators (model, test)

Semiconductor Models

MOS 11 by Geoffrey Coram (model, test)

Junction diode by Marek Mierzwinski (model, test)

Simplified junction diodes (dg-vams3-11, dg-vams3-12)

JFET by Geoffrey Coram (model, test)

Varistor by Geoffrey Coram (model, test)

Varactor (model, test, documentation)

FBH HBT by Matthias Rudolph (vers. 2.1) (model, listing, documentation, package)

Off-Site Models – Original Model Source

RF Models

These models are all free of hidden state and so will work with SpectreRF.

Periodic track and hold (model, test)

D flip flops (models, test)

Frequency divider (model, test)

Lossy capacitor (models, documentation)

Lossy inductor (models, documentation, dg-vams3-28)

Multidisciplinary Models

Verilog-AMS Model Library

Basic Models

Inverter (dg-vams4-1, dg-vams4-3)

Clock generator (dg-vams4-4)

D flip flop (dg-vams4-5)

Latch (dg-vams4-6)

Counter (dg-vams4-7)

Frequency measurement (dg-vams4-8)

Connect Modules

Electrical-to-logic connect modules (dg-vams4-16, dg-vams4-17)

Digital-to-analog connect module (dg-vams4-18)

Bidirectional connect modules (dg-vams4-19, dg-vams4-20)

Functional Models

Data converters (dg-vams4-9, dg-vams4-12)

Digital controlled switches (dg-vams4-10, dg-vams4-11)

Voltage controlled oscillator (dg-vams4-13)

Comparator (dg-vams4-14)

Phase-locked loop (dg-vamsA-4, dg-vamsA-10)

Disclaimer

Permission to make copies of these models for personal or classroom use is granted without fee provided that the copies are not made or distributed for profit or commercial advantage. To distribute otherwise, to publish, to post on servers, or to distribute to lists, requires prior written permission of the author.
These models are offered as is without warranty. By downloading these files, you agree not to hold either the authors or distributors of the models liable for consequential or incidental damages of any nature whatsoever that results from the use of these models.
Submit models for the Verilog-A/MS model libraries or requests for models by sending them to submit@designers-guide.org.

Extract models from .tgz files using "tar -zxvf filename.tgz".

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