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Sensitivity-driven design (Read 9355 times)
Ken Kundert
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Sensitivity-driven design
Jul 17th, 2005, 9:51am
 
In http://www.designers-guide.org/Forum/?board=circuit;action=display;num=110069063... Stephan suggests that the simulator should be able to perform a sensitivity analysis to determine which nodes are most sensitive to layout parasitics.

That seems like a very useful little feature than none of the vendors offer.

-Ken
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sheldon
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Re: Sensitivity-driven design
Reply #1 - Sep 23rd, 2005, 9:50am
 
Ken,

 Could you clarify the type of sensitivity you are looking
for? For example, Virtuoso's VAVO/VAEO give you the
sensitivity to parastic resistance, IR drop, and the sensitivity
to electromigration failure, em analysis. Were you looking
for sensitivity of circuit performance to layout parasitics?

                                                   Best Regards,

                                                      Sheldon
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Ken Kundert
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Re: Sensitivity-driven design
Reply #2 - Sep 23rd, 2005, 10:56pm
 
Nice. But VAVO/VAEO? It sounds more like a 70's rock band than a CAD tool.

are we not men? we are VAVO!
are we not men? V-A-E-O

-Ken
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Andrew Beckett
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Re: Sensitivity-driven design
Reply #3 - Sep 24th, 2005, 3:27am
 
And strictly speaking VAVO/VAEO don't tell you the sensitivity to the IR drop/EM issues. They allow you to analyse the circuit and find out what the IR drop is at various nodes in the circuit, or find EM failures. Not quite the same thing as seeing a sensitivity (IMHO). Still pretty useful though!

I liked Ken's views on the names though! They're just acronyms, because as engineers we don't like long marketing type names. They actually stand for:

Virtuoso Analog Voltagestorm Option
Virtuoso Analog Electronstorm Option

Rather boring really. I preferred the rock bands  ;)

Andrew.
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sheldon
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Re: Sensitivity-driven design
Reply #4 - Oct 3rd, 2005, 5:35am
 
Andrew,

  Guess it is a matter of perspective. Since the tool
provides IR drops plotted on the "extracted" layout,
effectively, it provides you the sensitive regions in the
layout.  If you always follow good design practices,
differential signal paths, star grounds, routing bias
currents, etc, then the regions with noisy power supplies
are most likely regions where there are supply noise
issues.

 Back to the original question, there was a technology
from OpMaxx --> Fluence --> IMS --> Credence called
DesignMaxx that calculated the sensitivities of the
circuit matrix using the adjoint matrix. This technology
would allow you to quickly calculate the sensitivities
of the output to the nodes in the circuit. However,
aren't there some issues with this approach? For
example, do all parameters have the same sensitivity
to layout parasitics? Or do you need to do a sensitivity
analysis for each design parameter? How are you going
to capture and use the layout constraints, particularly,
if the each parameter is sensitive to the parasitics at
different nodes?

  To look at the problem the other way around, why
aren't there tools for analog virtual prototyping? Doesn't
it make more sense to concurrently design the circuit
and the layout? Maybe it is just me but it seems like
the best solution to this problem is to be proactive,
i.e., use analog virtual prototyping.

                                                    Best Regards,

                                                         Sheldon

P.S.
For more information on the DesignMaxx approach, see
IEEExplore and search for limsoft, that was the name
of the Analog BIST tool DesignMaxx was integrated into.      
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weber8722
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Re: Sensitivity-driven design
Reply #5 - Nov 18th, 2011, 1:16am
 
Hi again

Ken Kundert wrote on Jul 17th, 2005, 9:51am:
In http://www.designers-guide.org/Forum/?board=circuit;action=display;num=110069063... Stephan suggests that the simulator should be able to perform a sensitivity analysis to determine which nodes are most sensitive to layout parasitics.

That seems like a very useful little feature than none of the vendors offer.

-Ken


I think in RF design or general analog design it would be good to see how much e.g. the gain at a certain frequency changes (or phase-margin or S12, etc.) from the presence of a parasitic C (or R or L) on a specific net.
In Cadence Parasitic-Aware Design flow there is the option to sweep parasitics, but only globally.
Recently we made a 5GHz LNA design, and the performance changed dramatically in RLC extracted view! So a designer need to find out, in which parts of the design the routing has the most impact.

Bye Stephan
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