Hi,

in a large analog CMOS block (basically an amplifier) we want to find out which of the circuit nodes needs the most careful layout, i.e. with minimum parasitic capacitance to subtrate. For instance one can add a 10fF cap at each node and switch it on and off, perform an AC simulation and looking at closed loop gain peaking of phase margin or step response overshoot.

However, how to automate this? My expectation was that there should be already something like that with Spectre's sens analysis, but there wasn't. In tran analysis you have cmin, which is quite nicce, but only related to all nodes simultaneously.

In my opinion sensitivity analysis is quite important in therory, but ADE implementation really keeps the users away of using it! Instead designers use parametric sweeps, but here is the danger that you are often not aware which parameters are important and need to be sweept.

Any ideas??[email][/email]

Bye Stephan