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animotion

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Req example of pulldown command in VerilogA
Dec 02^nd, 2011, 10:04am

Forum Users,

I need to model a pulldown function in VerilogA.

When the cntrl signal is high, this closes a mosfet switch and the signal of interest is then pulled to ground. This is the circuitry that I must model.

I am aware that there is a pulldown function in VerilogA (correct me if I am wrong). However, I do not know how to use the function.

Can someone please provide an example here that shows how to use it?

animotion

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Geoffrey_Coram

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Re: Req example of pulldown command in VerilogA
Reply #1 - Dec 5^th, 2011, 1:21pm

pulldowns are mentioned in the Verilog-AMS LRM, but I don't think of them as being part of Verilog-A.

The syntax is:
pulldown [pulldown_strength] pull_gate_instance { , pull_gate_instance };
pull_gate_instance ::= [ name_of_gate_instance ] ( output_terminal )
pulldown_strength ::=
( strength0 , strength1 )
| ( strength1 , strength0 )
| ( strength0 )

So:

pulldown pd1 (out);

would instantiate a pulldown named "pd1" on the node "out"

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boe Community Fellow Offline Posts: 615	Re: Req example of pulldown command in VerilogA Reply #2 - Dec 6^th, 2011, 4:52am Geoffrey, the pulldown of Verilog-AMS is digital, so it won't work in Verilog-A. I suggest a resistor to GND. - B O E
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animotion New Member Offline Posts: 4	Re: Req example of pulldown command in VerilogA Reply #3 - Dec 6^th, 2011, 8:34am BOE Thank you for the reply. How do I write the resistor to ground to model the circuitry that I describe? animotion
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animotion New Member Offline Posts: 4	Re: Req example of pulldown command in VerilogA Reply #4 - Dec 6^th, 2011, 8:47am Geoffrey & BOE The VerilogA LRM lists pulldown as a VerilogA HDL keyword in the Appendix but it does not give an example of is use. The code that Geoffery gives may apply to VerilogA too. I will try this with the cntrl on the mosfet tested in an if statement. Paul
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animotion New Member Offline Posts: 4	Re: Req example of pulldown command in VerilogA Reply #5 - Dec 6^th, 2011, 10:37am The pulldown as described is not working for me in VerilogA. I am willing to try out the resistor to ground if either of you could show me the code.
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boe Community Fellow Offline Posts: 615	Re: Req example of pulldown command in VerilogA Reply #6 - Dec 6^th, 2011, 10:57am You could try something like: Code: V(out) <+ I(out)*transition( (V(cntrl)>VDD/2) ? 1/Ron : 1/Roff, 1n); - B O E
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