Hey everyone,

Does anyone have a good experience with the instantiation of different cells in the same verilogams file?

I'm building a testbench and want to instantiate two instances that have the same name but exist in different libraries, one is schematic and the other one is veriloga.

What I did is the following:
     cell1
     (*
     integer library_binding = "Lib1";
     integer view_binding = "veriloga";
     *) dutvams (
           .x(dutvams_x),
           .y(dutvams_y),
           .z(dutvams_z)
     );
     cell2
     (*
     integer library_binding = "Lib2";
     integer view_binding = "schematic";
     *) dutsch (
           .x(dutsch _x),
           .y(dutsch _y),
           .z(dutsch _z)
     );
I'm also including the path to the veriloga model at the beginning of the verilogams file.

What happens is that when it compiles, it ignores the attributes in between the asterisks completely no matter what I'm tossing in, would only generate syntax errors if it's wrong and generates two schematic instances for Lib2.

When I change the name of the veriloga cell to a different name than the one for the schematic, it works properly.

I don't know what I'm missing here! Any help would be appreciated, thanks

Thanks Geo for your reply!
I'm using virtuoso IC6.1.6 and I think the syntax that I used is the one supported in the simulator. Could there be a check box or something to enable to get this attributes working?

I solved the problem, it needed a config file to go through the elaboration phase. I was working on the VerilogAMS Editor and the Extract button on it seems to only compile the code without elaborating it. The update button on the hierarchy editor does it properly. Thanks everyone!