The Designer's Guide Community
Forum
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
Apr 25th, 2024, 9:44pm
Pages: 1
Send Topic Print
If-Else in VerilogA- Designing memory element. (Read 10088 times)
Nishtha
New Member
*
Offline



Posts: 6

If-Else in VerilogA- Designing memory element.
Feb 15th, 2016, 8:09pm
 
Hello,

I am trying to design a memory element using VerilogA. In the case where the voltage goes between +Vtmax and -Vtmax, the code doesnt remember the previous value of x and the control directly jumps to else statement. How can I make it remember the previous value of x? Below is a piece of my code:

 analog
   begin
         `INITIAL_MODEL

       begin

x=0;
end

x = V(state);

if (V(G,S) >= Vtmax) begin      
                 R=Rp;
                 V(D) <+ I(D)* Rp;
                 x= 0;
                       end

else if (V(G,S) <= -Vtmax)  begin      
                 R=Rap;
                 V(D) <+ I(D)* Rap;
                 x= 1;                  
                 end
else if ( -Vtmax < V(G,S) < Vtmax)
                 begin
                       if(x==0) begin
                             R=Rap;
                             V(D) <+ I(D)* Rap;
                             x= 1;
                             
                             end
                       else if (x==1) begin
                             R=Rp;
                             V(D) <+ I(D)* Rp;
                             x= 0;
                             
                             end
                       else                        
                       V(D) <+ 0;
                 end
else   V(D) <+ 0;                    
V(state)<+ x;
end
endmodule  

Please help me on this.
Back to top
 
 
View Profile   IP Logged
Geoffrey_Coram
Senior Fellow
******
Offline



Posts: 1998
Massachusetts, USA
Re: If-Else in VerilogA- Designing memory element.
Reply #1 - Feb 16th, 2016, 12:50pm
 
It's very difficult to read your code as you have posted it; did you try using the "code" tag?  (For me, the button on the top row with # on it will put in the code and /code tags, which allows for better control of indentation.)
Back to top
 
 

If at first you do succeed, STOP, raise your standards, and stop wasting your time.
View Profile WWW   IP Logged
Geoffrey_Coram
Senior Fellow
******
Offline



Posts: 1998
Massachusetts, USA
Re: If-Else in VerilogA- Designing memory element.
Reply #2 - Feb 16th, 2016, 12:51pm
 
This isn't legal Verilog-A:
Quote:
else if ( -Vtmax < V(G,S) < Vtmax)
Back to top
 
 

If at first you do succeed, STOP, raise your standards, and stop wasting your time.
View Profile WWW   IP Logged
Geoffrey_Coram
Senior Fellow
******
Offline



Posts: 1998
Massachusetts, USA
Re: If-Else in VerilogA- Designing memory element.
Reply #3 - Feb 16th, 2016, 12:59pm
 
It looks to me that this assignment:
x = V(state);
is superfluous, because x always gets assigned a value of 0 or 1 in one of the if/else blocks:

if (V(G,S) >= Vtmax) begin
else if (V(G,S) <= -Vtmax)  begin
else if ( -Vtmax < V(G,S) < Vtmax)
else // what's left ???

other than the fact that the 3rd condition isn't legal Verilog-A syntax.
Back to top
 
 

If at first you do succeed, STOP, raise your standards, and stop wasting your time.
View Profile WWW   IP Logged
Ken Kundert
Global Moderator
*****
Offline



Posts: 2384
Silicon Valley
Re: If-Else in VerilogA- Designing memory element.
Reply #4 - Feb 16th, 2016, 2:05pm
 
Nishtha,
   If you want people to help you you should try to make it easy for them to do so. Posting a large, poorly formatted block of code that has no comments or explanation and is incomplete makes it very difficult to help. Kudos to Geoffrey for at least trying. I stared at your post for about 15 minutes and gave up.

When asking questions about code you should:
1. Try to boil down your code so that it is as small and simple as possible to make it easy to others to understand it.
2. Use the # (code) tag so that formatting is retained.
3. Properly format you code.
4. Send the complete model so that someone could copy and paste into a file and try it if need by. When you leave stuff out, you may just leave out the real problem. Remember, you don't understand what is going on, that is why you are asking questions, and so you may not have the best judgment of what can be safely left out.
5. Explain your code.

If you do all that, you just might find that you can answer your question yourself. If not, you are much more likely to get a helpful response.

-Ken
Back to top
 
 
View Profile WWW   IP Logged
Nishtha
New Member
*
Offline



Posts: 6

Re: If-Else in VerilogA- Designing memory element.
Reply #5 - Feb 16th, 2016, 6:10pm
 
I deeply apologize for the mistakes in my post.

My aim is to model a device in VerilogA which acts as an inverter and also has memory in it. I will correct the mistakes in code, try to fix the issues and if it still doesn't work, I will post a properly formatted version of the code here. I apologize again.

Best,
Nishtha

Back to top
 
 
View Profile   IP Logged
Nishtha
New Member
*
Offline



Posts: 6

Re: If-Else in VerilogA- Designing memory element.
Reply #6 - Feb 16th, 2016, 9:04pm
 
Hello,

I followed your guidance line by line and I was able to solve the issue. My code works fine now. Thanks a lot!

Best,
Nishtha
Ken Kundert wrote on Feb 16th, 2016, 2:05pm:
Nishtha,
   If you want people to help you you should try to make it easy for them to do so. Posting a large, poorly formatted block of code that has no comments or explanation and is incomplete makes it very difficult to help. Kudos to Geoffrey for at least trying. I stared at your post for about 15 minutes and gave up.

When asking questions about code you should:
1. Try to boil down your code so that it is as small and simple as possible to make it easy to others to understand it.
2. Use the # (code) tag so that formatting is retained.
3. Properly format you code.
4. Send the complete model so that someone could copy and paste into a file and try it if need by. When you leave stuff out, you may just leave out the real problem. Remember, you don't understand what is going on, that is why you are asking questions, and so you may not have the best judgment of what can be safely left out.
5. Explain your code.

If you do all that, you just might find that you can answer your question yourself. If not, you are much more likely to get a helpful response.

-Ken

Back to top
 
 
View Profile   IP Logged
Nishtha
New Member
*
Offline



Posts: 6

Re: If-Else in VerilogA- Designing memory element.
Reply #7 - Feb 16th, 2016, 9:06pm
 
Hello,

Thanks a lot for the reply. After fixing the below stated issues, I was able to get to a point where I was able to find the discrepancy in the code. Thank you so much!  I will post the updated code here if anyone wants to refer to it. Thanks!

Best,
nishtha

Geoffrey_Coram wrote on Feb 16th, 2016, 12:59pm:
It looks to me that this assignment:
x = V(state);
is superfluous, because x always gets assigned a value of 0 or 1 in one of the if/else blocks:

if (V(G,S) >= Vtmax) begin
else if (V(G,S) <= -Vtmax)  begin
else if ( -Vtmax < V(G,S) < Vtmax)
else // what's left ???

other than the fact that the 3rd condition isn't legal Verilog-A syntax.

Back to top
 
 
View Profile   IP Logged
Noah1988
New Member
*
Offline



Posts: 3

Re: If-Else in VerilogA- Designing memory element.
Reply #8 - Apr 20th, 2016, 1:42am
 
Nishtha wrote on Feb 16th, 2016, 9:06pm:
Hello,

Thanks a lot for the reply. After fixing the below stated issues, I was able to get to a point where I was able to find the discrepancy in the code. Thank you so much!  I will post the updated code here if anyone wants to refer to it. Thanks!

Best,
nishtha

Geoffrey_Coram wrote on Feb 16th, 2016, 12:59pm:
It looks to me that this assignment:
x = V(state);
is superfluous, because x always gets assigned a value of 0 or 1 in one of the if/else blocks:

if (V(G,S) >= Vtmax) begin
else if (V(G,S) <= -Vtmax)  begin
else if ( -Vtmax < V(G,S) < Vtmax)
else // what's left ???

other than the fact that the 3rd condition isn't legal Verilog-A syntax.



Could you please post the updated code and also point out where the error was at?
Back to top
 
 
View Profile   IP Logged
Pages: 1
Send Topic Print
Copyright 2002-2024 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.