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Problem of transition delay used in DTC verilog-A model (Read 194 times)

Hamlee

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Problem of transition delay used in DTC verilog-A model
Dec 28^th, 2015, 8:21pm

Dear all,

I am modeling a digital to time converter(DTC) using verilog-a code, and I met a negative delay problem. The spectre simulator always terminated when the DELAY move from a larger delay(say DELAY=100ps) to a small delay(say DELAY=20ps). Adding a fixed delay before DELAY will solve the problem, but I do not expect this fixed delay in my circuit design. Is there any better way to solve my problem?

Best regards,
Code:

`include "constants.vams"
`include "disciplines.vams"

module VERILOGA_DTC_11BIT(DIN, IN, OUT);
input [10:0] DIN;
input IN;
output OUT;
electrical [10:0] DIN;
electrical IN, OUT;

parameter tres = 300f;
parameter tr = 50p;
parameter tf = 50p;
parameter real Vhigh = 1;
parameter real Vlow = 0;

real DELAY, VIN, vout, Vtrans;

analog begin
	DELAY = (V(DIN[10])*1024+V(DIN[9])*512+V(DIN[8])*256+V(DIN[7])*128+
		 V(DIN[6])*64+V(DIN[5])*32+V(DIN[4])*16+V(DIN[3])*8+V(DIN[2])*4+
		 V(DIN[1])*2+V(DIN[0])*1)*tres;
	@(initial_step) begin
		vout = 0;
		Vtrans = (Vhigh+Vlow)/2;
	end

	@(cross(V(IN)-Vtrans, +1)) begin
		vout = Vhigh;
	end
	@(cross(V(IN)-Vtrans,-1)) begin
		vout = Vlow;
	end

	V(OUT) <+ transition(vout, DELAY, tr, tf);
end
endmodule

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Ken Kundert Global Moderator Offline Posts: 2384 Silicon Valley	Re: Problem of transition delay used in DTC verilog-A model Reply #1 - Dec 28^th, 2015, 10:28pm Spectre should not have any trouble with a decreasing delay. Perhaps you can show the results. -Ken
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Hamlee

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Re: Problem of transition delay used in DTC verilog-A model
Reply #2 - Dec 29^th, 2015, 8:59pm

Dear Kundert,

Thanks for your reply and suggestion. In simulation, if I keep increasing the delay (say DELAY = 10ps, 20ps, 30ps ....), it seems no problem at all. But if I decrease the delay (say DELAY = 320ps, 3ps), the error shows up. I attached the error message from spectreverilog simulator.

Capture_010.PNG

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Ken Kundert Global Moderator Offline Posts: 2384 Silicon Valley	Re: Problem of transition delay used in DTC verilog-A model Reply #3 - Dec 30^th, 2015, 10:54pm It seems like a good error message. Have you tried bounding the delay so that it does not go negative? -Ken
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Hamlee New Member Offline Posts: 5 Tokyo	Re: Problem of transition delay used in DTC verilog-A model Reply #4 - Jan 5^th, 2016, 3:40am Dear Kundert, Thanks for your reminding. I finally realized my problem that I used an unbounded delay in transition statement. It will cause the delay go negative but the transition expression does not support the negative delay statement. I bounded the delay and it works!
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Geoffrey_Coram Senior Fellow Offline Posts: 1998 Massachusetts, USA	Re: Problem of transition delay used in DTC verilog-A model Reply #5 - Jan 5^th, 2016, 6:24am How are you getting a negative value for DELAY? Are some of the voltages dipping below zero (perhaps briefly due to capacitive coupling)?
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Hamlee New Member Offline Posts: 5 Tokyo	Re: Problem of transition delay used in DTC verilog-A model Reply #6 - Jan 5^th, 2016, 7:00am Hi, There was no negative DELAY generated. The negative delay error in spectre shown in figure is owing to the unbounded DELAY in my verilog-a code. I added a fixed delay of 500ps to DELAY, then it works. I am not sue I understand your question precisely, plz ask me if you are not asking this.
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Geoffrey_Coram

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Re: Problem of transition delay used in DTC verilog-A model
Reply #7 - Jan 5^th, 2016, 11:34am

In your previous post, you wrote:
> I bounded the delay and it works!
but just now you wrote:
> I added a fixed delay of 500ps to DELAY, then it works.

Which is it?

For the first, I'd expect something like

�if (DELAY < 0) DELAY = 0;
�else if (DELAY > MAXDELAY) DELAY = MAXDELAY;

whereas the second would be just

�DELAY = DELAY + 500p;

In either case, what was the original value of DELAY computed from your formula?

Code:

DELAY = (V(DIN[10])*1024+V(DIN[9])*512+V(DIN[8])*256+V(DIN[7])*128+
		 V(DIN[6])*64+V(DIN[5])*32+V(DIN[4])*16+V(DIN[3])*8+V(DIN[2])*4+
		 V(DIN[1])*2+V(DIN[0])*1)*tres;

If V(DIN[i]) is between 0 and 1, then wouldn't DELAY be between 0 and 2047*tres? It doesn't seem like you'd need bounding -- unless V(DIN[i]) isn't between 0 and 1.

If at first you do succeed, STOP, raise your standards, and stop wasting your time.

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Ken Kundert

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Re: Problem of transition delay used in DTC verilog-A model
Reply #8 - Jan 5^th, 2016, 10:47pm

It look like he is intending to convert the binary value of a bus to a delay value, but that is not what the following line does:
Code:

DELAY = (V(DIN[10])*1024+V(DIN[9])*512+V(DIN[8])*256+V(DIN[7])*128+
	V(DIN[6])*64+V(DIN[5])*32+V(DIN[4])*16+V(DIN[3])*8+V(DIN[2])*4+
	V(DIN[1])*2+V(DIN[0])*1)*tres;

He is multiplying the voltage of each bit line by a power of two, but he should apply a threshold before multiplying by the power of two:
Code:

DELAY = (V(DIN[10] > Vth)*1024+V(DIN[9] > Vth)*512+V(DIN[8] > Vth)*256+V(DIN[7] > Vth)*128+
	V(DIN[6] > Vth)*64+V(DIN[5] > Vth)*32+V(DIN[4] > Vth)*16+V(DIN[3] > Vth)*8+V(DIN[2] > Vth)*4+
	V(DIN[1] > Vth)*2+V(DIN[0] > Vth)*1)*tres;

With his code, if V(DIN[10]) has overshoot and goes below zero, then the delay can go below zero.

-Ken

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Geoffrey_Coram Senior Fellow Offline Posts: 1998 Massachusetts, USA	Re: Problem of transition delay used in DTC verilog-A model Reply #9 - Jan 6^th, 2016, 7:36am That's what I was trying to get him to consider -- not just blindly bounding the result or adding a fixed extra delay, but understanding where the problem comes from. That fixed extra delay might not be sufficient for other simulations.
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Ken Kundert Global Moderator Offline Posts: 2384 Silicon Valley	Re: Problem of transition delay used in DTC verilog-A model Reply #10 - Jan 6^th, 2016, 9:04am Well it worked for me. I did not see the problem until your question. -Ken
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Hamlee

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Re: Problem of transition delay used in DTC verilog-A model
Reply #11 - Jan 7^th, 2016, 3:33pm

Dear Geoffrey,

I think my last post is not correct. You are right, I added a 500ps delay to DALAY which make the error gone. But this is not the expected way the circuit should work. I corrected the code. Thanks for your question. It really made me think this question again.

Code:

@(cross(V(IN)-Vtrans, +1)) begin
		DELAY = (V(DIN[10])*1024+V(DIN[9])*512+V(DIN[8])*256+V(DIN[7])*128+
		 V(DIN[6])*64+V(DIN[5])*32+V(DIN[4])*16+V(DIN[3])*8+V(DIN[2])*4+
		 V(DIN[1])*2+V(DIN[0])*1)*tres;
		vout = Vhigh;
	end
	@(cross(V(IN)-Vtrans,-1)) begin
		DELAY = (V(DIN[10])*1024+V(DIN[9])*512+V(DIN[8])*256+V(DIN[7])*128+
		 V(DIN[6])*64+V(DIN[5])*32+V(DIN[4])*16+V(DIN[3])*8+V(DIN[2])*4+
		 V(DIN[1])*2+V(DIN[0])*1)*tres;
		vout = Vlow;
	end
	  V(OUT) <+ transition(vout, DELAY, tr, tf);

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Geoffrey_Coram

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Re: Problem of transition delay used in DTC verilog-A model
Reply #12 - Jan 14^th, 2016, 5:20am

I think this is probably a significant improvement, only changing the value of DELAY when there's a crossing. It's much less likely that the DIN voltages will have strange values at those few crossing times.

However, I think Ken's suggestion of using a threshold like (V(DIN[10] > vth) would still be a good idea, also.

If at first you do succeed, STOP, raise your standards, and stop wasting your time.

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