sourav
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Posts: 7
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Hi,
i want to design a gated current source. Here i have used a simple current mirror topology. Current through PM12 and PM13 will be controlled through the signal phi1 and phi2. Before adding these switches i was getting current 128 times of 40nA as I fixed the W/L ratio 128 times of PM10 and PM11. After adding the switches i was expecting current only during the on time of phi2 and zero value when it is off. I have taken here ideal switches and they are implemented in Verilog A with on resistance of 1ohm and Off resistance of 100Mohm. i am using gpdk 180nm technology file in cadence. after the simulation i am getting an unstable current instead of constant current. i have observed several times that whenever i am using some clock in mos circuits it generates some random fluctuation in current at the other terminals.
please tell me the reason behind it and give me some suggestion
thanks
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