I suppose you could construct a Verilog-AMS module using $bound_step to control the timestep in particular sections:

module tcontrol();
real the_time, tmax;
analog begin
 the_time = $abstime;
 if (the_time < 1u)
  tmax = 10m;
 else if (the_time < 1.1u)
  tmax = 1p;
 else if (the_time < 2u)
  tmax = 10m;
// ...
 $bound_step(tmax);
end
endmodule

Hi Emmanuele,

I like Geoofrey's solution and I would encourage you going forward with it. If you don't want using an AMS module, then you can control some analog parameters of your simulation during the simulation itself. It is a manual approach that requires running AMS Designer in interactive mode, i.e. using the Simvision GUI to control the simulation.

From the simvision console, run
Code:

ncsim> help analog 

This would tell you all the analog options you can set, this includes the reltol option which defaults to 1e-3 off the top of my head.

All what you need to setup the a new value for reltol is
1. launch the simulator with a very short stop time. The aim here is to invoke the simulator. Say :
Quote:

2. Run the following to see the current options:
Quote:

3. Alter the value of reltol for example:
Quote:

4. Run the simulation for the desired time, say 1us
Quote:

5. Alter the reltol to a new value and run again.

I can't really remember whether you need to play with the 'analog -stop' option. Please give it a try as I'm offline at the minute.

Hope this helps,

Regards,
Riad.

I don't know what "AMS Simulator" is, but if it's a simulator that supports Verilog-AMS, then my approach should work.

I've never written anything in Design HDL, so I don't know if the functions you need are available in the language.  Cadence tools generally support Verilog-AMS, you just need to learn how to take the code I've given you and make your simulator use it.