Mayank wrote on Dec 13^th, 2009, 9:50pm:
The following relation is well known.
   SNR=-10*log₁₀[2/(3*2^Nbit) + {2*pi*fin*Tsj/sqrt(2)}²]
   Here Nbit=Resolution Bits of ADC, fin=Frequency of Input Signal, Tsj=Peak Value of Sampling Jitter

Search application notes of ADI or TI(Burr Brown)

Mayank wrote on Dec 13^th, 2009, 9:50pm:
I can't understand a meaning of your question.
Please explain in detail with using correct terminologies.

There are many methods for evaluation of ADC SNR
Most simple method for evaluation of ADC SNR is FFT.
I think answer is self-obvious.

hi mayank,
                i feel it's longtem jitter, because in ADC variation in sampling instant will degrade your SNR, so in this regard long term jitter you have to consider. but in your second post i didn't understand ''Cycle-to-Cycle Period Jitter depends mostly on VCO+LoopFilter and is not corrected by the PLL. While Long-Term Period Jitter is corrected by the PLL , is dependent on PLL BW & noise contibutions from cpump/pfd/dividers/reference etc.''

Thanks,
Rajasekhar.

Hi all,

@ raja : Quote:

Two Points :--
1.   Variation in each Sampling Instant is Cycle-to-Cycle Jitter.
2.   Variation in a Sampling Instant of a Nth Sample wrt to a particular Sample will fall in Long-Term Jitter.

@ Pancho :  I would like to mention Sir that i am still in designing Phase...Unfortunately, i dont have any test-chip of my design that i can test for. But i will keep your points in mind when i do actual testing. Coming Back to my query,

Quote:


Edge-to-Edge Jitter metric is always used in those circuits which are driven by an external clock,in our case the ADC, whose clock comes from the output clock of my PLL. So, The Cycle-to-Cycle Jitter of the PLL Output Clock forms the Edge-to-Edge Jitter for sampling clock of ADC. Is This opinion Correct ???

Two More Questions :---

Also, The Cycle-to-Cycle Jitter of a PLL is given simply by the VCO + LF Phase Noise, as indicated in Ken's Paper http://www.designers-guide.org/Analysis/PLLnoise+jitter.pdf equations (63) & (74) on page on page 31 & 32 respectively. Am i correct ??

When I integrate the output phase noise curve of a PLL & obtain rms phase error & corresponding Jitter in Time domain by multiplying rms Ph. error by Tosc/2/pi ,  What i get is Long-Term PLL Jitter right ??  
This post makes me think i am correct -- http://www.designers-guide.org/Forum/YaBB.pl?num=1236788112/0#5


Quote:
This is the Oscillator Line-Width that is indicated by Cadence Spectre in Output Log & also marked as Corner Frequency in a 'Phase Noise' plot in 'pnoise' option of Direct Plot Form....I Just placed a Marker at that Frequency.

--regards,
Mayank.

Hi Pancho,

Quote:

I am talking about Locked State of a PLL itself.
Even in the Locked State of a PLL, the Cycle-to-Cycle Jitter is determined by the VCO + LF itself because PLL Loop being slow, say slower than nearly 1000 times the VCO Frequency, cannot correct Cycle-to-Cycle Jitter which is a measure absolute jitter b/w two consecutive time periods.
You can view this as ---> Within PLL BW, PLL Low-Passes & limits Oscillator Jitter. After PLL BW, PLL Phase Noise plot tracks the Oscillator Phase Noise which means that after PLL Loop BW, PLL can't correct the Jiiter
     However, PLL can correct long-term jitter which is average Jitter of a Nth edge wrt to a particular edge, because there the slow PLL Loop corrects & maintains Jitter within Bounds.

Quote:

By This statement, i understand that you are referring to Long-Term Jitter as absolute Jitter.
Reasoning for my belief - Because in case of a Free-running VCO, Long-Term Jitter goes Unbounded as there's No Loop/Mechanism to Correct it, as is indicated by the inceasing Pnoise with decreasing Freq Offset in a  Pnoise Plot of Free-running Osci. But in a PLL, this osci pnoise being low-passed is bounded and you can get a limit on Long-Term Jitter. Correct ??

But Anyways, Cycle-to-Cycle Jitter has nothing to do with Integration/accumulation of Jitter & Hence can still be defined for Both.

--
regards,
Mayank.

Hello Pancho,
   
Point understood and taken.
But then if i know the sampling Jitter requirements for the ADC which acc. to you is the simple Timing Jitter wrt an external/reference frequency,   How do i put a spec on PLL output Jitter and which metric should i put a spec on -- Long-Term / Cycle-to-Cycle / Absolute Jitter of a PLL ??  

+  How do i measure absolute Jitter in a PLL in simulations / EDA Tool Play  :P ??   because i am yet not at fab/test-chip stage.

--Mayank.

Hi guys,

I think this is the best discussion I have ever seen about the this topic, jitter measurement of PLL and sampling jitter of ADC.  

When I test ADC, the signal generator for clock and input are locked together. I think the primary cause is to keep a coherent sampling in the test. If the two signal sources (for clock and signal) has correlated jitter in long term, they will cancel each other partly.

Pancho said,
Quote:


No, this is not true absolute jitter. It is more like a tracking jitter. The measured jitter depends on the difference between the reference clock and the PLL output.  The big problem is that the tracking jitter isn't what we need in ADC application. In real application, the signal source is not locked to the reference clock of the PLL (sampling clock source).  I mean that the input signal is not related to the sampling clock usually. So only absolute jitter (maybe we can call it long-term jitter, too) play his role to affect ADC SNR. Even the real application is not the same as what we do in the test.



Best Regards,
Yawei

Hello Guys,
     
So It being said that Absolute Jitter is the correct metric for ADC Sampling clock......How should i compute the absolute Jitter for the PLL, i mean through EDA Tool PLay ??

--
regards,
Mayank