Thanks a lot for your help, Mr. Coram.
The first method you mentioned works well, namely, calculating the circuit's total power by multiplying the voltage and current in the
analog block of the excitation source module (whether it is voltage or current source).
The second method is really subtle and delicate. I mean, the skillful
I(input1,input1a). It works well both for resistor load or capacitor load even without explicitly define the branch.
However, when I applied the second method to the 6 order inverter case, shown as following, Hspice refuses to work and doesn't give any message. I have two questions.
(1)I wonder whether it is because the inverter is implemented by calling a subcircuit of inverter in Hspice, which cause some confusion for the simulator.
(2)If so, I tried to implement the inverter in Verilog-a.
From your discussion in a former thread (
http://www.designers-guide.org/Forum/YaBB.pl?num=1274466479), I found your paper on the 2014 conference and BSIM4v5. To avoid my self-written probably bad code, I want to use the BSIM4v5 directly in Verilog-a module. But the BSIM4v5 are written in C. So is it possible to call it in Verilog-a and conduct simulation in Hspice?
Thanks in advance.
The module to calculate the power of inverter is as following.
Code:module test_inv6_power_ref_v21(input1, output1, vdd_chain, gnd_chain, vinpwr, vddpwr, sourpwr, invpwr);
inout input1, output1, vdd_chain, gnd_chain;
output sourpwr,vinpwr, vddpwr, invpwr;
electrical input1, output1, vdd_chain, gnd_chain, sourpwr,vinpwr;
electrical vddpwr, invpwr;
electrical input1a, vdd_chaina;
ground gnd;
parameter freq=1e8, vcc_volt=1;
//Instantiate the inverter chain in HSPICE subcircuit
inverter_chain_6order inverter_chain(input1a, output1, vdd_chaina, gnd_chain);
//Signal voltage source
volt_pwl_osc1_pwrout #(.freq(freq)) voltsour_pwlout(input1,gnd,vinpwr);
//Vcc and Gnd voltage source
vsrc_dc_pwrout #(.dc(vcc_volt)) vcc_drive(vdd_chain, gnd,vddpwr);
vsrc_dc #(.dc(0)) gnd_drive(gnd_chain,gnd);.
analog begin
V(invpwr,gnd) <+ V(input1a,gnd)*I(input1,input1a) + V(vdd_chaina,gnd)*I(vdd_chain,vdd_chaina);
end
endmodule