Hello all,
  I am designing the clock generation circuit for a pipeline ADC and I have some conceptual questions about methods for verifying the jitter performance of my circuit.

  If I understood correctly, one way to measure jitter in spectre is to run pss, save the bias point of all xtors at the time instant the final output buffer stage reaches a certain threshold, linearize the circuit about the bias point, and compute the power spectral density at the output of the linearized circuit.  The integral of the power spectral density over all frequency then gives the noise variance at the buffer output at the time instant  the output reaches a certain threshold.  An estimate for jitter can then be obtained by computing sqrt(noise variance)/(slew rate).

  However, doesnt this method assume that other than the time instant when output hits threshold the buffer output was completely free from noise?  In reality, at the onset of a clock transition, noise would be throwing the "trajectory" of the output voltage off from its noise-free trajectory; and the longer it takes the clock to transition, the more the trajectory gets thrown off its course.  So it seems noise behavior over the entire clock transition from start to threshold should be somehow accounted for when we compute noise variance, and not just consider noise variance at the time when output reaches threshold.  Also, if this were true, it seems estimating jitter by pss would underestimate jitter.

Thanks in advance!

Hi Ken,
  But isn't the method described in your paper the same as what I described?  You wrote on p. 29 that "the statitistics of nv are only significant at the time when vn(t) crosses the threshold.  So you computed Jee=(noise variance)/(slew rate)^2 using the noise variance at the time instant when vn(t) crosses threshold.  But by doing so, arent we disregarding the contribution of the noise at time instances prior to crossing threshold?

-Badminton

I'd like to add further to this debate. Badmington is querying whether there is an accumulation of jitter prior to the crossing point but still on the crossing slope. Ken is saying yes there is but what about even earlier in time when circuits are hardswitched at limits prior to the onset of crossing? I have a ripple divider (described in an earlier thread) and I want to know that when I use the strobed pnoise technique to obtain a total phase noise result that when I divide the total output noise of the whole divider chain by the (slew rate)^2 and divide by the final divided down period 1/(w^2) (eq 35 in PLLnoise+jitter.pdf above) I do obtain the accumulated phase noise ? Each stage is a SCL CML divider with reduced current in each stage as the freqeuency is halved.

To test that the simulator does accumulate jitter or phase noise from earlier stages I knocked up a testbench with a whole string of inverters and divided them into 4 groups. A PSS time plot showed none of the crossovers from each group overlapped in time with the next group. I measured the phase noise using the strobed method and eq 35 from Ken's document to obtain the phase noise at each group output. I wanted to know if the final output phase noise was influenced by the earlier inverter groups in the chain despite being hard switched at the time of the crossover point of the last inverter output. I found that the output of the 4th group phase noise plot was worse than the 1st group phase noise plot by 6dB (25%) and again worse than the 2nd gropup by 3dB (50%) and again worse than the 3rd group by 1.2dB (75%). So it seems there was a jitter accumulation despite the earlier stage being hard switched at the time of the final stage crossover.

Is my finding correct?

Thank you Frank. Very handy to know. I think I need to go on a Cadence refresh course as they have sneaked alot of new options in to the various simulators lately!