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Cadence Sample Library - cell names?? (Read 5781 times)
Pavel
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Cadence Sample Library - cell names??
Oct 23rd, 2006, 7:50am
 
Hello

In Cadence Verilog-AMS Language Reference there is chapter "Sample Model Library".
In this chapter one can find all the Verilog-A internal primitives with terminals and parameters,
but NOT the NAMES of modules. How could I instantnate them?

For example I need Schottky diode.
In above-mentionned Doc I find the following:

Schottky Diode

Terminals
vanode: anode voltage [V,A]
vcathode: cathode voltage [V,A]

Description
This model is of a diode based on the Schockley equation.
Instance Parameters
area = area of junction
.....

But what is the module name of Schottky diode?

Another question - where in Cadence installation could I find the Verilog-A codes of "Sample Module Library" modules?

Thank in advance.

Pavel
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Pavel
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Re: Cadence Sample Library - cell names??
Reply #1 - Oct 23rd, 2006, 9:09am
 
OK, resolved.

The primitives are in:
$CDSHOME/tools/dfII/samples/artist/spectreHDL/Verilog-A/
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Pavel
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Re: Cadence Sample Library - cell names??
Reply #2 - Oct 27th, 2006, 1:25am
 
Situation is more complicated than I thought.

Ok, source code is localized, but can one use it without supplimental library declaraion in cds.lib.
For example how to instantiate nmos, pmos primitives?
I found MOS primitives in $CDSHOME/tools/dfII/samples/artist/ahdlLib/mos_level1.
But when I try insantiate it:

mos_level1 MP #(.length(10u), .width(10u)) MN1

the cell isn't recognized.
What I do - I create MOS cell (veriloga view) in library and copy mos_level1 veriloga code.
But I think it isn't "smart" approach.

So original question persists - how instantiate the primitives from Cadence Sample Model Library.
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Andrew Beckett
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Re: Cadence Sample Library - cell names??
Reply #3 - Oct 28th, 2006, 1:40pm
 
From your append, it sounds as if you're not putting a reference in the cds.lib - you'll need to do that:

Code:
DEFINE ahdlLib $(inst_root_with:tools/dfII/bin/icfb)/tools/dfII/samples/artist/ahdlLib 



(the inst_root_with incantation is to avoid having to reference an environment variable - it finds it in the installation root containing icfb).

Having done that, you should be able to reference it.

Regards,

Andrew.
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Pavel
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Re: Cadence Sample Library - cell names??
Reply #4 - Oct 30th, 2006, 7:52am
 
Thank you for answer Andrew.

Could you explain me what are resistor and capacitor?
There are no such primitives in ahdlLib library, they don't apear in Verilog-A Keyword list.
Nevertheless I can instantiate these "primitives"

capacitor #(.c(10p)) C1 (A, B);
resistor #(.r(10k)) R1(A, B);

and they are recognized without any supplimental actions.

Best Regards.

Pavel.
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Ken Kundert
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Re: Cadence Sample Library - cell names??
Reply #5 - Oct 30th, 2006, 8:06am
 
resistor and capacitor are built-in primitives for Spectre.

-Ken
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Pavel
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Re: Cadence Sample Library - cell names??
Reply #6 - Oct 30th, 2006, 8:32am
 
Thank you for answer Ken.

Where could I find the full list of Spectre primitives with terminals/parameters:

Regards.

Pabel.
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bernd
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Re: Cadence Sample Library - cell names??
Reply #7 - Oct 30th, 2006, 11:00am
 
In the "Virtuoso Spectre Circuit Simulator Components and Device Models Manual"
<install_dir>/doc/spectremod/spectremod.pdf,
or if you prefer command line help "spectre -h".


Bernd
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Geoffrey_Coram
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Re: Cadence Sample Library - cell names??
Reply #8 - Nov 1st, 2006, 4:09am
 
Ken Kundert wrote on Oct 30th, 2006, 8:06am:
resistor and capacitor are built-in primitives for Spectre.


Ken -
That's only half the answer.  The other point is that "resistor" and "capacitor" are listed explicitly in Annex E of the Verilog-AMS Language Reference manual, which talks about Spice compatibility.  For those Spice primitives listed in Annex E, simulators are supposed to map instantiations in a Verilog-style netlist into the built-in primitives (regardless of whether the Spice simulator calls those primitives by the same names).

For Pavel, it may or may not be useful to see the whole list of Spectre primitives, since some of them can't be instantiated in a Verilog netlist (or module definition) because they require a model (eg bjt, mosfet).  Annex E doesn't cover how one tells the simulator to find the model cards in a Spice-format library file.

-Geoffrey
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Pavel
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Re: Cadence Sample Library - cell names??
Reply #9 - Nov 6th, 2006, 12:01am
 
In my version of Verilog-AMS Language Reference manual (5.5.1, August 2005) there are no keywords "resistor" and "capacitor"  in Annex E "Verilog-A Keywords". But there are many others, that are just listed, but don't explained. For example cmos, nmos, pmos, rnmos, rpmos, etc...

What they signify, all these keywords?

Regards.

Pavel.
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Geoffrey_Coram
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Re: Cadence Sample Library - cell names??
Reply #10 - Nov 6th, 2006, 6:06am
 
Pavel wrote on Nov 6th, 2006, 12:01am:
In my version of Verilog-AMS Language Reference manual (5.5.1, August 2005) there are no keywords "resistor" and "capacitor"  in Annex E "Verilog-A Keywords". But there are many others, that are just listed, but don't explained. For example cmos, nmos, pmos, rnmos, rpmos, etc...

What they signify, all these keywords?


5.5.1 is not a valid version number.  The official Accellera Verilog-AMS LRM is presently on version 2.2, dated September 2004.  In the true LRM,
Annex E is "SPICE Compatibility" and Annex B is "Keywords" and includes cmos, nmos, ... which are explained in the IEEE 1364 Verilog LRM (the AMS LRM was based on the 1995 version of the 1364 standard, which has since issued a 2005 edition).

I'd be curious to know where you got the LRM that claimed to be an official one.  Perhaps you are looking at the Verilog-AMS documentation for your simulator, as opposed to the LRM.

-Geoffrey
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Pavel
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Re: Cadence Sample Library - cell names??
Reply #11 - Nov 6th, 2006, 7:58am
 
Ok, Geoffrey

I found cmos, nmos, ...  in IEEE 1364 standard.
Concerning your last question, please have a glance on picture.

Regards.

Pavel.
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Cadence_AMS_1st_page.JPG
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Geoffrey_Coram
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Re: Cadence Sample Library - cell names??
Reply #12 - Nov 6th, 2006, 12:32pm
 
So, indeed, you have vendor-supplied documentation.

For the offical LRM, please visit http://www.eda.org/verilog-ams and click on the "Download LRM" button on the left side.

-Geoffrey
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