Hi folks,
            I was simulating a transistor (65nm, with BSIM4) in cadence spectre. I did a parmteric DC run and then plotted Cgd. It was negative !
Beats me really. I guess its model thats causing prob?? Any comments?
  Cheers

           

The next-generation "PSP" model (http://pspmodel.asu.edu) addresses many of the oddities in the BSIM3/4 models such as negative capacitance.

I wouldn't say "no worries" -- there have been some convergence failures caused by negative capacitances in series with positive resistors yielding an unstable system.

Achim is right, though, that you should look in the manual, make sure that the sign conventions are what you expect.  Eg, many simulators define cgd as -dQg/dVd.

Hi jefkat,
             dont know about 65nm, but when looking at 90nm and 180nm mos CV curves I found that spectre got it wrong, but both Hspice and WinSPICE3 got it right.  At least, the results were consitent between different foundary models and matched tht measured on the bench.

For DC sims, capacitance has no practical meaning; use AC or TRAN.

Apply a voltage source to the gate using a line like:

     Vg      G S DC {Vgs} AC 1 PWL(0 {-dv} {dt} {dv})

For AC scale the frequency sweep for (say) 159kHz using a line like:

ac lin 2 159k 159.3k

or for TRAN scale it by choosing the parameters dv and dt, then plot the current through the capacitor for TRAN:

Cg[index] = abs(vg#branch)*{dt}/{2*dv}

or the AC output current using a line like:

Cg[index] = abs(vg#branch)/(2*PI*159.3e3)

You wont be able to do the tran version in spectre as it does not make the last simulation values available to you (at least not easily).  
Hspice or WinSPICE3 do this nicely and you can be sure the results are as you would use the model in practice - there are PDKs around for well known foundries that give wildly different values for capacitance when simulated under DC, AC and Tran!

Cheers,
           SimonH.

Hi Geoffrey,
                  I meant that at DC (0 Hz) the capacitance has no effect on current through a node.  You need a change in voltage to get a response, thus only AC or Tran have any real meaning in a practical application.  Agreed, you can extract all sorts of information from static models by interrogating their equations, but I am not sure to what you would apply the results.  I have also found that looking at say gate capacitance under OP then sweeping bias point and taking OPs at each point generally for most simulators produces a flat line at some arbitrary capacitance value which often is grossly in error with respect to that you will get from an AC or TRAN sim at each bias point, or if you compare it to measured data for the modelled device.  My guess is that the simulators are not intended to support DC or OP sims for capacitance in any serious way, as at DC (0 Hz), the result you see is possibly the product of legacy code in the underlying (SPICE) algorithm.

Cheers,
           Simon2.

Hi Geoffrey, re:

> You have to be careful about extracting the capacitance from an ac analysis,
> since having internal resistors (RD, RS) in the model will confuse the issue:
> dQg/dVd is wrt the internal drain voltage, but the voltage source is applied
> to the external terminal.

- are we not just interested in the imaginary part of the current?  
- or did I misunderstand what you meant?

Cheers, Simon2.