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mxkdirs

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TieDowns
Mar 06^th, 2006, 8:50am

Can some one explain the concept of tie downs to me? Exactly how are they done? The design kit I'm using says that I need to connect both the plates of my MIM caps. The way I read it, it seems like the signal will shunt to ground/substrate if I connect my plates to a diffusion. Now I read somewhere that you do reverse bias connection but I'm not sure how to create one or how to go about doing so. Any help will be much appreciated. Thanks

-mike

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ACWWong

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Re: TieDowns
Reply #1 - Mar 7^th, 2006, 8:56am

Hi Mike,

You need to tie down the plates of a MIM to avoid charge build up during processing causing damage to thin dielectric of the MIM.
You do this by adding a tiedown diode to the MIM plates. So if you are in a grounded p-substrate you need to connect the MIM plates to n-diffusion (in the p-substrate) such that it creates a reversed biased diode to substrate. The diodes acts as charge leakage path during processing to avoid MIM dielectric breakdown. Additionally the diode will add a small parasitic capacitance, and as it is a diode you will get less parasitic capacitance the further reversed biased it is. Generally your design kit will tell you if you have made the tiedown big enough (to aviod MIM manufacturing problems), and what parasitic C it has added.
You can of course create the diode by tieing the plates to p diffusion in an n-well. Then in this case, to ensure no forward biasing problem of the tiedown diode, your nwell should be at the highest potential on the chip.

Cheers
alan

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Croaker Senior Member Offline Posts: 235	Re: TieDowns Reply #2 - Mar 7^th, 2006, 2:50pm Alan, good answer. So it sounds pretty much like the problem that inspires 'antenna rules' for big pieces of metal connected to MOS gates. Cheers, Marc
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ACWWong

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Re: TieDowns
Reply #3 - Mar 8^th, 2006, 2:02am

Hi marc,

yes, its very much akin to the normal antenna rules for FET gates...
Infact a few different foundries i have designed in using thin dielectric MIM have stipulated that the bottom metal plate MUST wire up to the metal above/contact metal for top plate (although not actually the top plate metal which is generally inter-metal layer) before coming back down and connecting to the circuit. In that way both plates are kept at the same potential during processing.

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Paul

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Re: TieDowns
Reply #4 - Mar 8^th, 2006, 12:14pm

Hi Alan and Marc,

Very interesting thread indeed. I wasn't aware of this problem as the process I am currently using is purely digital and doesn't offer MiM caps. I use vertical fringing caps which do not exactly deliver the same density compared to MIM, but are quite linear too (and become better with each process generation :)).

I wonder whether you would expect any leakage issues due to the tie-down diodes in switched-cap circuits, which would be a typical application for MiM caps? Of course the wiring Alan describes in the last post is a good work-around, if accepted by the foundry (and supported by the DRC deck...).

Thanks for sharing your experience.

Paul

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mxkdirs

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Re: TieDowns
Reply #5 - Mar 9^th, 2006, 7:49am

Thanks for all your posts. I understand now what's going on now. So, are you saying the bigger the n+ diffusion (I have p substrate) the lower the parasitic capacitance? I know different design kits would have different values but I was wondering if someone knows on what order of parasitic capacitance is generated due to tie downs? I couldn't find a value in my design manual. I'm little bit concerned because I've some very small value shunt caps (~100-200 fF) used in my matching networks and the tolerance for them is no more than 20%, meaning the parastics should be no more than 1.2 times the value in my design. Thanks

-Mike

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ACWWong

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Re: TieDowns
Reply #6 - Mar 9^th, 2006, 2:35pm

hi mike

no, the smaller the n+ diffusion in the p substrate, the smaller the parasitic capacitor. so you should add as small a tiedown as possible (your DRC or Antenna rule deck will tell you what is required).

What can reduce the capacitance is if the reverse bias is greater (reduced depletion capacitance).... that is you get a smaller value of parasitic due to the tiedown if the n diffusion (and therefore the MIM plates) is biased at a voltage nearer vdd than ground.

Having said that if the N diffusion is only about 1umx1um then the parasitic C we are likely to be talking about is only a couple of fF (exact number should be availbe in your PDK or RCX extraction deck). given your MIM cap is 100~200 fF and assuming 1~3fF/um2 density, i'd be surprised if you need an antenna diode much greater than 1umx1um ....

cheers

alan

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jxbvt

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Re: TieDowns
Reply #7 - Mar 13^th, 2006, 2:07pm

Hi Alan,

Thanks a lot for your feedback. Great answer. You're right--in fact, I need only .5x.5 um^2 of area. One thing though about the diodes being reversed bias. Hope this doesn't sound dumb. The fact is that the MIMs I'm really concerened about are at my input and output matches, meaning there's no DC there so how is the bias of those diodes connected to MIM plates quantified? Meaning, the DC is blocked so how's reverse biasing of diode determined?? Thanks

-mike

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Croaker

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Re: TieDowns
Reply #8 - Mar 14^th, 2006, 8:06am

Paul wrote on Mar 8^th, 2006, 12:14pm:

Hi Alan and Marc,

Very interesting thread indeed. I wasn't aware of this problem as the process I am currently using is purely digital and doesn't offer MiM caps. I use vertical fringing caps which do not exactly deliver the same density compared to MIM, but are quite linear too (and become better with each process generation :)).

I wonder whether you would expect any leakage issues due to the tie-down diodes in switched-cap circuits, which would be a typical application for MiM caps? Of course the wiring Alan describes in the last post is a good work-around, if accepted by the foundry (and supported by the DRC deck...).

Thanks for sharing your experience.

Paul

I actually just used MiM caps in a 90-nm process and they didn't require tiedowns.

I would imagine that the tiedowns are eventually going to drain the charge from any capacitive node. In quasi-floating gate circuits there is a reverse diode to make the high impedance connection and it definitely drains charge.

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ACWWong

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Re: TieDowns
Reply #9 - Mar 14^th, 2006, 8:14am

hi mike,

Where-ever the MIM is connected in the circuit or to a pad, there will be some voltage on the plates, be it transient or DC. The issue of reverse bias means that if you use a MIM plate tiedown (n diffusion in grounded p substrate), you must ensure that the transient voltages on do not go below ground by more than diode drop (~0.6 V) else the tiedown will conduct (forward bias).
The further above ground the voltage (therefore n +ve wrt to p gnd), the lower the reversed biased diode's capacitance.

cheers
alan

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