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Random data signal in cadence (Read 6012 times)
rjshmadala
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Random data signal in cadence
Jan 12th, 2006, 8:37am
 
hello,
which signal in cadence should use to rpoduce a random  binary data input signal (0101010010010100101....)for  clock and data recovery circuits.(or)in D flip flop
Regards
Rjshmadala
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Andrew Beckett
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Re: Random data signal in cadence
Reply #1 - Jan 12th, 2006, 10:26am
 
If you use ahdlLib (in <instdir>/tools/dfII/samples/artist), there is a verilog-a model in there called rand_bit_stream - so you can use that.

Regards,

Andrew.
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Ken Kundert
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Re: Random data signal in cadence
Reply #2 - Jan 13th, 2006, 8:28am
 
You'll also find some random bit stream generators at verilog-ams.com.

-Ken
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gitarrelieber
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Re: Random data signal in cadence
Reply #3 - Apr 11th, 2006, 6:56am
 
Suggest to write a PRBS generator in verilog-a. Important is to implement the random sequence which can be sent by a bit error rate tester (BERT).
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Re: Random data signal in cadence
Reply #4 - Apr 15th, 2006, 2:26pm
 
The standard logical model of a prbs source is a simple shift register with a couple of OR gates on the appropriate bits to get a Maximal Length Sequence..

the tutorial here looks like a decent explanation.
http://www.newwaveinstruments.com/resources/articles/m_sequence_linear_feedback_...

with some tables..

- in verilog A, once you have the Length you want, and the MLE polynomial,
just use an "integer" to hold the value , shift it left, and or the output (old MSB) with the selected bits to get  the new LSB..



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Re: Random data signal in cadence
Reply #5 - Apr 15th, 2006, 3:07pm
 
[font=Courier][/font]
for prbs 7
parameter integer xorbits = 3<<5;
parameter integer seed = 3;
integer code newbit bitcode i;
analog begin
...
...
  @(initial_step) begin
     code = seed;
  end
  @(timer(period, period)) begin
     newbit = 0;
     bitcode = (code & xorbits);
     ; now xor the results
     for (i=0; i<7 ; i = i+1) begin
       newbit = (newbit ^bitcode)&1;
       bitcode = bitcode >>1;
    end
    code = (code <<1)|newbit;
 end

...
V(out) <+ transistion((code&1? vhi: vlo), 0, tr, tf);

---
your milage may vary..
especially if your seed is right (ie All Zeros usually generates a minimal length )
or your pattern (1100000 in this case 3<<5) is not one of the ones from the table..
(which will mean that you don't get a Maximal Length sequence.. )

(imagine a pythonized version ? )

  @initial_step:
     code = seed;

  @timer start period repeat period:
     newbit = 0
     bitcode = (code & xorbits)
     # now xor the results
     for i in [0,1,2,3,4,5,6]
       newbit = (newbit ^bitcode)&1
       bitcode = bitcode >>1
    code = (code <<1)|newbit;
 V(out) <+ transition((code?vhi:vlo),0,tr)

   jbd
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gitarrelieber
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Re: Random data signal in cadence
Reply #6 - Apr 18th, 2006, 6:07am
 
Here is also a code example for PRBS generator.

// VerilogA for wk_hu, prbs_gen, veriloga

`include "constants.vams"
`include "disciplines.vams"

module prbs_gen(clkp, clkn, outx, outb);
input clkp, clkn;
output outx, outb;
voltage clkp, clkn, outx, outb;
parameter integer bit_num = 8 from [2:32];
parameter integer seed = 1 from [1:inf];

integer x, a1, a2, a3, a4, b, mask;
analog begin
  @(initial_step) begin
       case (1)
          (bit_num ==  2): begin a1=0; a2= 1; a3= 0; a4= 0; end // 2 [0,1]
            (bit_num ==  3): begin a1=0; a2= 2; a3= 0; a4= 0; end // 3 [0,2]
            (bit_num ==  4): begin a1=0; a2= 3; a3= 0; a4= 0; end // 4 [0,3]
            (bit_num ==  5): begin a1=1; a2= 4; a3= 0; a4= 0; end // 5 [1,4]
          (bit_num ==  6): begin a1=0; a2= 5; a3= 0; a4= 0; end // 6 [0,5]
            (bit_num ==  7): begin a1=0; a2= 6; a3= 0; a4= 0; end // 7 [0,6]
            (bit_num ==  8): begin a1=1; a2= 2; a3= 3; a4= 7; end // 8 [1,2,3,7]
            (bit_num ==  9): begin a1=3; a2= 8; a3= 0; a4= 0; end // 9 [3,8]
            (bit_num == 10): begin a1=2; a2= 9; a3= 0; a4= 0; end //10 [2,9]
            (bit_num == 11): begin a1=1; a2=10; a3= 0; a4= 0; end //11 [1,10]
          (bit_num == 12): begin a1=0; a2= 3; a3= 5; a4=11; end //12 [0,3,5,11]
            (bit_num == 13): begin a1=0; a2= 2; a3= 3; a4=12; end //13 [0,2,3,12]
            (bit_num == 14): begin a1=0; a2= 2; a3= 4; a4=13; end //14 [0,2,4,13]
            (bit_num == 15): begin a1=0; a2=14; a3= 0; a4= 0; end //15 [0,14]
          (bit_num == 16): begin a1=1; a2= 2; a3= 4; a4=15; end //16 [1,2,4,15]
            (bit_num == 17): begin a1=2; a2=16; a3= 0; a4= 0; end //17 [2,16]
            (bit_num == 18): begin a1=6; a2=17; a3= 0; a4= 0; end //18 [6,17]
            (bit_num == 19): begin a1=0; a2= 1; a3= 4; a4=18; end //19 [0,1,4,18]
          (bit_num == 20): begin a1=2; a2=19; a3= 0; a4= 0; end //20 [2,19]
            (bit_num == 21): begin a1=1; a2=20; a3= 0; a4= 0; end //21 [1,20]
            (bit_num == 22): begin a1=0; a2=21; a3= 0; a4= 0; end //22 [0,21]
          (bit_num == 23): begin a1=4; a2=22; a3= 0; a4= 0; end //23 [4,22]
          (bit_num == 24): begin a1=0; a2= 2; a3= 3; a4=23; end //24 [0,2,3,23]
          (bit_num == 25): begin a1=7; a2=25; a3= 0; a4= 0; end //25 [7,25]
            (bit_num == 26): begin a1=0; a2= 1; a3= 5; a4=25; end //26 [0,1,5,25]
          (bit_num == 27): begin a1=0; a2= 1; a3= 4; a4=26; end //27 [0,1,4,26]
            (bit_num == 28): begin a1=2; a2=27; a3= 0; a4= 0; end //28 [2,27]
            (bit_num == 29): begin a1=1; a2=28; a3= 0; a4= 0; end //29 [1,28]
            (bit_num == 30): begin a1=0; a2= 3; a3= 5; a4=29; end //30 [0,3,5,29]
          (bit_num == 31): begin a1=2; a2=30; a3= 0; a4= 0; end //31 [2,30]
            (bit_num == 32): begin a1=1; a2= 5; a3= 6; a4=31; end //32 [1,5,6,31]
            default $strobe("Error. Should never get here.");          
        endcase
        mask = pow(2, bit_num) -1;
      x = seed;
      x = x & mask; //mask the unavailable bit;
     
  end
 
  @(cross(V(clkp, clkn), +1, 10p)) begin
      b = ((x>>a1)^(x>>a2)^(x>>a3)^(x>>a4))%2;
      x = ((x<<1) & (mask-1)) + b;
  end
 
  V(outx) <+ x;
  V(outb) <+ b;
 
end

endmodule
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jbdavid
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Re: Random data signal in cadence
Reply #7 - Apr 21st, 2006, 1:10am
 
Its certainly several times the code of my model..
What theory is it based on? (always a good idea to put a reference to theory behind the model in a case like this.. )
what is the maximal lenght pattern ?

Jonathan
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Re: Random data signal in cadence
Reply #8 - Apr 24th, 2006, 5:00am
 
I coded the PRBS generator in this way so that different PRBS configuration (PRBS2..PRBS32) can be easily achieved by changing the module parameter bit_num. This is done in @(initial_step). The module parameter bit_num is the length of the linear feedback shift register (LFSR).

The variable x is the bits of the LFSR. The variable mask is used to mask the unused bits in x. For instance, if bit_num is 7, then the variable mask is equal to ...001111111b, which means only the last 7 bits of x is actually used and the unused bits are all set to 0. The variable a1, a2, a3 and a4 determine which bits of the LFSR should be XORed together and fed back. The feedback bit b is calculated as b = ((x>>a1)^(x>>a2)^(x>>a3)^(x>>a4))%2; The feedback bit b is added to the variable x as LSB.

The setting of [a1, a2, a3, a4] is copied from the webpage
http://www.maxim-ic.com/appnotes.cfm?appnote_number=1743&CMP=WP-9

The valid maximum run length is 32-bit. It is of course possible to extend the bit_num to more than 32. But I am not sure how many bits does an integer have in Verilog-A language.

I do not know whether Verilog-A language has the key word "generate" like VHDL, with which the bit number can be flexibly altered.
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Re: Random data signal in cadence
Reply #9 - Nov 18th, 2006, 6:50am
 
gitarrelieber wrote on Apr 18th, 2006, 6:07am:
Here is also a code example for PRBS generator.

// VerilogA for wk_hu, prbs_gen, veriloga

`include "constants.vams"
`include "disciplines.vams"

module prbs_gen(clkp, clkn, outx, outb);
input clkp, clkn;
output outx, outb;
voltage clkp, clkn, outx, outb;
parameter integer bit_num = 8 from [2:32];
parameter integer seed = 1 from [1:inf];

integer x, a1, a2, a3, a4, b, mask;
analog begin
  @(initial_step) begin
       case (1)
          (bit_num ==  2): begin a1=0; a2= 1; a3= 0; a4= 0; end // 2 [0,1]
            (bit_num ==  3): begin a1=0; a2= 2; a3= 0; a4= 0; end // 3 [0,2]
            (bit_num ==  4): begin a1=0; a2= 3; a3= 0; a4= 0; end // 4 [0,3]
            (bit_num ==  5): begin a1=1; a2= 4; a3= 0; a4= 0; end // 5 [1,4]
          (bit_num ==  6): begin a1=0; a2= 5; a3= 0; a4= 0; end // 6 [0,5]
            (bit_num ==  7): begin a1=0; a2= 6; a3= 0; a4= 0; end // 7 [0,6]
            (bit_num ==  8): begin a1=1; a2= 2; a3= 3; a4= 7; end // 8 [1,2,3,7]
            (bit_num ==  9): begin a1=3; a2= 8; a3= 0; a4= 0; end // 9 [3,8]
            (bit_num == 10): begin a1=2; a2= 9; a3= 0; a4= 0; end //10 [2,9]
            (bit_num == 11): begin a1=1; a2=10; a3= 0; a4= 0; end //11 [1,10]
          (bit_num == 12): begin a1=0; a2= 3; a3= 5; a4=11; end //12 [0,3,5,11]
            (bit_num == 13): begin a1=0; a2= 2; a3= 3; a4=12; end //13 [0,2,3,12]
            (bit_num == 14): begin a1=0; a2= 2; a3= 4; a4=13; end //14 [0,2,4,13]
            (bit_num == 15): begin a1=0; a2=14; a3= 0; a4= 0; end //15 [0,14]
          (bit_num == 16): begin a1=1; a2= 2; a3= 4; a4=15; end //16 [1,2,4,15]
            (bit_num == 17): begin a1=2; a2=16; a3= 0; a4= 0; end //17 [2,16]
            (bit_num == 18): begin a1=6; a2=17; a3= 0; a4= 0; end //18 [6,17]
            (bit_num == 19): begin a1=0; a2= 1; a3= 4; a4=18; end //19 [0,1,4,18]
          (bit_num == 20): begin a1=2; a2=19; a3= 0; a4= 0; end //20 [2,19]
            (bit_num == 21): begin a1=1; a2=20; a3= 0; a4= 0; end //21 [1,20]
            (bit_num == 22): begin a1=0; a2=21; a3= 0; a4= 0; end //22 [0,21]
          (bit_num == 23): begin a1=4; a2=22; a3= 0; a4= 0; end //23 [4,22]
          (bit_num == 24): begin a1=0; a2= 2; a3= 3; a4=23; end //24 [0,2,3,23]
          (bit_num == 25): begin a1=7; a2=25; a3= 0; a4= 0; end //25 [7,25]
            (bit_num == 26): begin a1=0; a2= 1; a3= 5; a4=25; end //26 [0,1,5,25]
          (bit_num == 27): begin a1=0; a2= 1; a3= 4; a4=26; end //27 [0,1,4,26]
            (bit_num == 28): begin a1=2; a2=27; a3= 0; a4= 0; end //28 [2,27]
            (bit_num == 29): begin a1=1; a2=28; a3= 0; a4= 0; end //29 [1,28]
            (bit_num == 30): begin a1=0; a2= 3; a3= 5; a4=29; end //30 [0,3,5,29]
          (bit_num == 31): begin a1=2; a2=30; a3= 0; a4= 0; end //31 [2,30]
            (bit_num == 32): begin a1=1; a2= 5; a3= 6; a4=31; end //32 [1,5,6,31]
            default $strobe("Error. Should never get here.");          
        endcase
        mask = pow(2, bit_num) -1;
      x = seed;
      x = x & mask; //mask the unavailable bit;
     
  end
 
  @(cross(V(clkp, clkn), +1, 10p)) begin
      b = ((x>>a1)^(x>>a2)^(x>>a3)^(x>>a4))%2;
      x = ((x<<1) & (mask-1)) + b;
  end
 
  V(outx) <+ x;
  V(outb) <+ b;
 
end

endmodule



I am curious how case(1) works? It seems no manual support such syntax?
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Re: Random data signal in cadence
Reply #10 - Dec 3rd, 2006, 8:36pm
 
>>I am curious how case(1) works? It seems no manual support such syntax?

case (arg)
looks for the first of the case statements whose value matches "arg"

so case (1)
looks for the first of the following statements that evaluates to "1" (or is True)
jbd

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