Help me!
Get me answer for sensitive issue. How can I connect VHDL-AMS/Verilog-AMS electrical/logical terminal to low level (transistor) analog circuitry for Cadence AMS Designer Environment. Please, give me advice for all cases.

We'll I had a gentler reply going but the page reset itself while I was writing it..
Please go look at www.bmas-conf.org
and see my Verilog-AMS  tutorial from 2002, or my more recent paper from 2004.. BTW MY stuff isn't the ONLY good stuff there..
Of course even BETTER would be to buy a copy of Ken's book from this site and get reading..

The Quick answer is "structural" modeling which can be combined with behavioral modeling..
and some of that I answered in a couple of posts last week.. (Note.. This is PROPERLY a topic for the Verilog-AMS language section!)
jonathan

Let me describe it another way, which might make things clearer. Verilog-AMS supports the idea of automatic connectmodule (a.k.a. interface elements) insertion at discipline boundaries. VHDL-AMS does not (it's a strongly typed language, and as a result, the "disciplines" of connected ports must match).

What that means is that we are free to insert connectmodules within Verilog-AMS code, but cannot do so in VHDL-AMS.

That said, the electrical disciplines in VHDL-AMS and Verilog-AMS match, and so these can be connected directly. Similarly the standard logic disciplines between the two languages match. Also, by adding a layer of Verilog around some VHDL/VHDL-AMS code (sometimes known as a "shell" or "wrapper"), you then have somewhere for the automatic connectmodule insertion to work.

This is a slightly simplistic view of things, but hopefully should be clear enough to answer your questions by explaining how it works rather than answering the specific question and giving you no understanding of why.

Regards,

Andrew.

Please, one more question. When I connect two VHDL_AMS terminals with electrical disciplines (branch) to spectre resitor I have mistake on elaboration stage. Why. Does electrical discipline of VHDL-AMS is fully supported by Cadence AMS Designer?

In detail:
// Verilog-AMS netlist generated by the AMS netlister, version 5.0.33_USR1.35.4.
// Cadence Design Systems, Inc.

`include "disciplines.vams"
`include "constants.vams"

module test (  );


resistor #(.r(1K))  (* integer library_binding = "analogLib";  *) R0
( cds_globals.\gnd! , net1 );

generator  (* integer library_binding = "testlib";  *) I0 ( .aout( net1 ),
.ref( cds_globals.\gnd!  ) );

endmodule

This is test VHDL-AMS generator description:
library ieee, std;
use ieee.std_logic_1164.all;
use ieee.electrical_systems.all;

entity generator is
     generic (
     ULO : real := 0.2; -- output voltage for logic '0'
     UX : real := 2.5; -- output voltage for logic unknown or high-impedance
     UHI : real := 4.8; -- output voltage for logic '1'
     RON : real := 0.1; -- internal resistance for strong states
     RWK : real := 1.0e4; -- internal resistance for weak states
     ROF : real := 1.0e9; -- internal resistance for high-impedance state
     TT : real := 1.0e-9); -- output transition time
     port (
           terminal aout, ref: electrical); -- analog outputs
end generator;

architecture bhv of generator is
     type real_table is array (std_logic) of real;
     constant R_table: real_table := (RON, RON, RON, RON, ROF, RWK, RWK, RWK, ROF);
     constant V_table: real_table := (UX, UX, ULO, UHI, UX, UX, ULO, UHI, UX);
     quantity uout across iout through aout to ref;
     signal reff: real := 0.0; -- effective resistance
     signal veff: real := 0.0; -- effective voltage
     signal din: std_logic := '0'; -- logic input
     begin
           din <= not din after 10us;
           reff <= R_table(din);
           veff <= V_table(din);
           uout == veff'ramp(TT) + iout*reff'ramp(TT); -- iout is defined from aout to ref
end architecture bhv;

Thanks...