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bal New Member Offline Posts: 2	verilog A code for 16:1 mux Feb 14^th, 2010, 2:26pm i need a verilog A code for 16:1 mux ..thank you
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pancho_hideboo Senior Fellow Offline Posts: 1424 Real Homeless	Re: verilog A code for 16:1 mux Reply #1 - Feb 15^th, 2010, 2:00am http://www.designers-guide.org/Forum/YaBB.pl?num=1260351750/5#5 If you have Cadence Spectre, see "ahdlLib/multiplexer". You can easily modify this code to create 16:1 Mux. Here use "case ~ endcase" statement in Verilog-A code.
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bal

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Re: verilog A code for 16:1 mux
Reply #2 - Feb 15^th, 2010, 4:13am

since its a 16:1 i have 4 select pins which i have declared it is as input pins .. so these ports cannot be used for binary to decimal conversion in further logic .. As u told ,a case statement should be used , but before using that i need find a way such that i must covert all 4 bits to decimal value store in a variable and use it in a case statement. If u could tell me a logic for above problem i can use the case statement and select the inputs . thank you..

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pancho_hideboo

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Re: verilog A code for 16:1 mux
Reply #3 - Feb 15^th, 2010, 4:20am

There are many methods to use binary expression for case statement.

For example, see http://www.designers-guide.org/Forum/YaBB.pl?num=1265985977

Code:

`define �Nbits � � 4
input [`Nbits-1:0] sel;
voltage [`Nbits-1:0] sel;

parameter real Vth=1.5;
integer logic_value[0:`Nbits-1];
integer sel_value;

genvar i;

analog begin

sel_value = 0;
for(i=0; i <=`Nbits-1; i=i+1) begin
 � �logic_value[i] = (V(sel[i]) > Vth) ? 1 : 0;
 � �sel_value = sel_value + logic_value[i]*(1<<i);
end

case(sel_value)
 � .....
endcase

end

Read documents of Verilog-A surely.

Attached is an example for conventional usage of case statement.

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conventional_case.png

« Last Edit: Feb 16^th, 2010, 2:54am by pancho_hideboo »

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pancho_hideboo Senior Fellow Offline Posts: 1424 Real Homeless	Re: verilog A code for 16:1 mux Reply #4 - Feb 15^th, 2010, 4:35am Attached is another example for usage of binary data in case statement. ( (logic_value[3]==1) && (logic_value[2]==1) && (logic_value[1]==0) && (logic_value[0]==1) ) : "statement";
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