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trond

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low frequency phase noise peculiarity in fractional N-PLL
Jan 06^th, 2009, 6:35am

I have dual-path PLL verilogA model and use it to obtain the phase noise. When plotting the phase noise at the output of the feedback divider (~26MHz) I obtain the blue plot shown in the figure.

As expected we see a 40dB/decade slope as the sigma delta is of order 3. However, there is lots of low frequency "noise" which I cannot account for. I was expecting the red curve.

Does anyone have an idea where this noise might arise from?
I am pretty sure it has something to do with the input to the feedback divider being itself a modulated frequency (by the sigma delta) instead of a constant vco frequency. But I fail to see the relationship.

BTW, all models are ideal and contain no non-linearity or additional jitter.

Thanks,

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trond

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Re: low frequency phase noise peculiarity in fractional N-PLL
Reply #1 - Jan 8^th, 2009, 5:35am

After some more poking around I ended up looking at the SDM output via some different Matlab FFT routines which average the data points to compute the PSD.

I have attached a figure (blue plot) which shows the SDM o/p spectrum with a pwelch routine. Being no DSP expert I would assume that due to the averaging of different FFTs and windowing (with a finite SNR) the noise floor at low frequency remains constant.

Can i now assume that something similar happens in the PLL loop which would explain why the phase noise plot of the divider output (red curve) comes up again?

Any feedback is appreciated.
Cheers,

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Aigneryu

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Re: low frequency phase noise peculiarity in fractional N-PLL
Reply #2 - Jan 9^th, 2009, 9:21pm

Just first make sure one thing, the red curve is open loop (fixed input VCO frequency and divided by a divider which is modulated by DSM). and the blue curve is when the PLL is in closed-loop. Is it correct?

Are you using a tri-state PFD-CP in your model or an ideal linear phase detector (simple substraction function between two input phases)?

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trond Senior Member Offline Posts: 168 Glasgow, Scotland	Re: low frequency phase noise peculiarity in fractional N-PLL Reply #3 - Jan 9^th, 2009, 9:42pm Aigneryu, Yes you are correct. In the first plot the red one is essentiall the phase noise of the divider driven with a fixed VCO frequency. Essentially open loop. The red curve in the first post is from a closed loop simulation. I am using a linear PFD/CP. No tristate is used. Cheers,
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Aigneryu

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Re: low frequency phase noise peculiarity in fractional N-PLL
Reply #4 - Jan 11^th, 2009, 1:02pm

There could be some issues which depend on how the simulation is performed.

If your open-loop result is derived, the close-in phase noise can be very low. For example, the integer numbers are first obtained from a DSM, then use phase=2*pi*cumsum(inst_divisor-ave_divisor)/ave_divisor.

If a behavioral VCO is used to drive the DSM, and then the periods are extracted based on edge (or zero-crossing) detection, and the phases are then derived from those periods, the close-in phase noise will not have the ideal shape since numerical error due to the transient timing can introduce a 1/f^2 roll-off to the VCO phases which again drives the DSM.

Are you using spectre to run the simulation?

Sincerely,
Shih-an

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trond

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Re: low frequency phase noise peculiarity in fractional N-PLL
Reply #5 - Jan 11^th, 2009, 11:50pm

Aigneryu,

Thanks for your feedback.

Aigneryu wrote on Jan 11^th, 2009, 1:02pm:

If a behavioral VCO is used to drive the DSM, and then the periods are extracted based on edge (or zero-crossing) detection, and the phases are then derived from those periods, the close-in phase noise will not have the ideal shape since numerical error due to the transient timing can introduce a 1/f^2 roll-off to the VCO phases which again drives the DSM.

So are we saying that errors such as the tolerances in using the @(cross) statement in VerilogA and/or transient simulation step size will result in 1/f^2 noise?

But when using the same behavioral VCO with a constant input voltage (and hence o/p frequency) and FBdivider at its output I do not get the low frequency noise.

Yes I am using Spectre.

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Aigneryu

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Re: low frequency phase noise peculiarity in fractional N-PLL
Reply #6 - Jan 12^th, 2009, 3:04pm

Can you tell me how many points, timing tolerance you use, divided frequency?

I brought up this tolerance issue is because, from what I can see in my simulations, using an "ideal" simulation without any numerical noise (use integers from the DSM and compute the phases) and using a behavioral VCO model with a fixed tune voltage and a DSM can already introduce ~20dB difference in noise floor. I use typical settings in analog options, but with conservative transient, and the time steps are bounded by 0.625ns when the divided frequency is 16MHz.

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Aigneryu

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Re: low frequency phase noise peculiarity in fractional N-PLL
Reply #7 - Jan 12^th, 2009, 4:38pm

Another question, what is your loop bandwidth of the PLL?

Since you are extracting the phases of the feedback divider, you need to take into account the filtering of the PLL. In this case, the forward gain is unity, and the loop gain is the same as the closed-loop PLL. However, this still cannot explain the results you got since, in principle, we should see a highpass characteristic.

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trond

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Re: low frequency phase noise peculiarity in fractional N-PLL
Reply #8 - Jan 13^th, 2009, 10:28am

Initially I thought it might be tolerances or varying simulation time steps. Hence, I set the maxstep and stepsize to something like 1/26MHz/100 as my reference frequency is 26MHz. It did not make a difference.
The BW is the PLL is approx. 200kHz.

I am sure it has something to do with the o/p frequency of the PLL being modulated by the SDM.

I tried one open loop simulation with a constant voltage into the VCO and hence a constant o/p frequency. As mentioned before the phase noise after the feedback divider is as expected.

In a second run I added some noise shaped quantization noise to the otherwise constant input voltage of the VCO. The quantization noise I added was the 3rd order noise from a SDM which I low pass filtered by a simple first RC filter. Again I observed the phase noise after the divider. Even though this was also an open loop simulation I got similar low frequency noise than in the closed loop sims. Hence, it should have something to do with the input of the feedback divider which is controlled by the SDM being itself modulated by the quantization noise of a SDM.

I cannot explain it however.
I'll have to think some more about this.....

Thanks for your responses Aigneryu.

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Aigneryu

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Re: low frequency phase noise peculiarity in fractional N-PLL
Reply #9 - Jan 13^th, 2009, 12:20pm

How you wrote your model? I did a quick check with a model which preserves all the asynchronous operaions in a PFD-CP PLL. I also extracted the phase infomation at the output of the divider, but I did not see such kind of difference.

These is difference if I use open loop to compare the ideal case.
But if I use transient to get both open loop phase or the closed loop phase at the output of div, it shows a hipass effect within the loop BW.
matlab "psd" function is used. (pwelch is the same if you further scale fs it)

I attached the fig for your reference.
Test case:
16MHz reference, 2.4GHz RF, loop BW=45kHz
N=150+536435/2^21. 3rd order MASH-111

The datalength is about 32.5ms(about 525k pts). And I use nfft=65536 pts, winLength=nfft/2, overlap=windLength*7/8

The green line is the ideal open loop phase
The red line is the DSM modulated divider open loop phase by trans
The black line is the DSM modulated divider closed loop phase by trans
The blue line is the output VCO phase in closed loop with a DSM modulated divider in the feedback path.

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Aigneryu Senior Member Offline Posts: 102	Re: low frequency phase noise peculiarity in fractional N-PLL Reply #10 - Jan 13^th, 2009, 12:26pm Another thing, I have not yet tried to use matlab to check what if the VCO cycle is jittery. I expect the green line will be become resemble to the red line.
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trond

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Re: low frequency phase noise peculiarity in fractional N-PLL
Reply #11 - Jan 14^th, 2009, 7:12am

Hello Aigneryu,

My model consists of standard verilogA models for each of the PLL components. See the attached figure for the overall PLL. As shown I combined the VCO and the feedback divider to increase the simulation speed. I write the lengths of each period for the VCO/N and the VCO/(N+y[n]) to a file and use Matlab to compute the phase noise. y[n] is the SDM output.

1) When you say you "preserve all the asynchronous operations in a PFD-CP PLL" what do you mean by that? It is not like there is an explicit sampler.

2) Your phase noise plot for the VCO closed loop o/p seems very low (blue line). Did you use the 2.4GHz signal to plot the phase noise? I would assume you used a divided down version of the VCO o/p but then have to scale it by the division^2 as the phase noise is reduced when dividing it down. Just checking.

3) Is your model one verilogA file, ie the whole PLL contained or do you have each block modeled and then connected in a schematic window?

I will put together a rar file with all the models and netlist to email if you like.

I noticed you run your transient simulation for a long time. So far I have only considered 2ms, hence, 52k samples. I will run it for longer to see if it makes a difference.

Cheers,

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Aigneryu

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Re: low frequency phase noise peculiarity in fractional N-PLL
Reply #12 - Jan 14^th, 2009, 9:12am

How did you model the DSM? Is y[n] from a DSM triggered by the reference clock or the divided clock (fbdiv)?

My model is written in all phase domain except for the cp current out.
By skipping the phase-to-voltage domain transition, the simulation be be slightly faster and more accurate from what I found in most of my designs.

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trond

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Re: low frequency phase noise peculiarity in fractional N-PLL
Reply #13 - Jan 14^th, 2009, 9:20pm

Since I was trying various SDM implementations I have all of my models in Matlab. I simply save the SDM o/p to a file and read in each value with the divided down clock into the PLL.

It could very well be that the voltage-to-phase conversion might introduce some additional errors. I will write a phase-model and see if my results will differ.

Thanks,

Ps. If not against IP mmaybe you can email me your phase model for comparison.

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« Last Edit: Jan 15^th, 2009, 6:35am by trond »

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walkingsun

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Re: low frequency phase noise peculiarity in fractional N-PLL
Reply #14 - Feb 16^th, 2009, 5:21am

Could you talk about your phase domain model ?

Aigneryu wrote on Jan 14^th, 2009, 9:12am:

How did you model the DSM? Is y[n] from a DSM triggered by the reference clock or the divided clock (fbdiv)?

My model is written in all phase domain except for the cp current out.
By skipping the phase-to-voltage domain transition, the simulation be be slightly faster and more accurate from what I found in most of my designs.

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