Sameer Kher wrote on Jan 11th, 2008, 1:28pm:didac, all,
With VHDL-AMS, you either specify the process sensitivity list or have appropriate wait statements to ensure that your process is correctly triggered. So the code should work.
Perhaps you can verify that the problem is indeed only in the S&H model by using it by itself (assuming you are using it in a system). It may be an implementation bug in the software.
Good luck,
Sameer
yep, it is not working by itself,
maybe someone can share a working sample and hold code
thanks