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Upemba

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Running Switched-Capacitors simulation
Dec 04^th, 2007, 12:14pm

I am learning how to simulate switched-capacitor circuit using a PSS and then a PAC.
I am having trouble to duplicate the Ken Kundert example of the "Simple Track and Hold" circuit to run a PSS and then a PAC or PXF simulation. (example is described in the following document http://www.designers-guide.org/Analysis/sc-filters.pdf)

According to the documantation, the PSS must run first to determine the periodic operating point. After that, the periodic operating point will be saved and used as a starting point of PAC simulation.

My questions are: How do you run this kind of simulation? Ken uses an "alter" statement to change the supply from dc to sine wave when going from PSS to PAC. Can some help me to walk through this process step by step?

Remember that I have never run a PSS before nor a PAC.
Thanks

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Ken Kundert

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Re: Running Switched-Capacitors simulation
Reply #1 - Dec 4^th, 2007, 6:41pm

PSS always runs before PAC. No alter statement is needed to apply the input in PAC. Just set pacmag=1 on the input source, that will provide a stimulus in PAC that is not present in the PSS.

In this way, PSS/PAC are like DC/AC in Spice. The DC analysis always runs before an AC analysis, and you specify mag=1 to provide the stimulus in AC and that stimulus is not present in the DC analysis.

-Ken

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Upemba

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Re: Running Switched-Capacitors simulation
Reply #2 - Dec 10^th, 2007, 9:08am

Ken,

Thanks for that feedback. That was very insightful.

However, I have further questions:

Running a PSS with multiple clocks ie. input stage clock is Fclk1 and output sampled clock is Fclk2 = Fclk1/8 to ADC. (decimation since the sample rate at the output is reduced). Now, I know that the PSS will run over a period of Tclk2=1/Fclk2=8*Tclk1 where Tclk1 is 1/Fclk1

Here is my question:

Does the PSS will also consider the fact that Tclk1 being the smallest period that will fit 8 times inside the period of Tclk2.
In other words, does the periodic operating point will be calculated over a period of Tclk1 or calculating the periodic operating point over a period of Tclk2 will cover Tclk1 as well?

P.S Please note that when I say input stage clock, it is not the input signal but the clock that is supposed to sample the input signal. Hope that makes sense to you. Thanks

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Ken Kundert Global Moderator Offline Posts: 2384 Silicon Valley	Re: Running Switched-Capacitors simulation Reply #3 - Dec 10^th, 2007, 10:46am You have to specify to the PSS analysis that the fundamental frequency is Fclk2 (the lower frequency). Once you do that the periodic operating point is computed over Tclk2. Of course, Fclk1 must be an exact multiple of Fclk2. Once you do this, all works as it should. -Ken
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Upemba

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Re: Running Switched-Capacitors simulation
Reply #4 - Dec 10^th, 2007, 1:59pm

Thanks Ken.

My follow up question is where do you specify that my fundamental frequency is Flck2 which is 400Hz?(Flck1=3.2KHz).
In the pss analysis page under Fundamental Tones, that page is filled up automatically from schematic. I called all the clocks "clock" (Flck1 and Flck2 since they are multiples) as you suggested but that was for qpss analysis.

Can you please help me on that?

Also can you elaborate on "number of harmonics" and so far I have set to 100. How do set that number?

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Ken Kundert Global Moderator Offline Posts: 2384 Silicon Valley	Re: Running Switched-Capacitors simulation Reply #5 - Dec 11^th, 2007, 1:18am Override Artist and force the fundamental frequency to 400kHz. Do not use QPSS. In PSS the number of harmonics does not control accuracy. Use it only to specify how many harmonics you would liked computed and saved simply because you might be interested in viewing them. -Ken
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Upemba

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Re: Running Switched-Capacitors simulation
Reply #6 - Dec 13^th, 2007, 1:59pm

Ken

I really appreciate the time you take to answer my questions. I am getting something that is working.
Just want to know (or double check) how to override Artist and force the fundamental at 400Hz.

Basically I am getting some results (transfer function) with a DC gain of 2.06 instead of 3.2 (from MATHCAD). I am trying to make sure that the low gain of 2.06 is due to other factors such as analog models othen than my simulation setup.

Thanks a lot.

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Upemba

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Re: Running Switched-Capacitors simulation
Reply #7 - Dec 19^th, 2007, 7:18am

I am running a pac (periodic AC) simulation on a SC integrator circuit and the dc gain that I am measuring is about 33% off from the value expected. In other word, I have to multiply the simulated gain value obtained by 1.5 to get the expected value. I know that the expected value is correct from transient simulation and also from MATHCAD calculation.
Since this is the first time that I am running SpectreRF to simulate this circuit, I am wondering if I am doing something wrong in my setup or this is a problem related to SpectreRF.
Please help.
Thanks

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Ken Kundert

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Re: Running Switched-Capacitors simulation
Reply #8 - Dec 19^th, 2007, 10:09am

Remember that PAC is computing the Fourier coefficients and reporting on those individually. Consider applying a 1Vp sine wave to the input. If the output is a clocked 1Vp sine wave, people often assume that the gain of the circuit is 1 because that is the way they think of it. But SpectreRF is computing the Fourier coefficients and coming to a different conclusion. The clocked sine wave often as a duty cycle of 50% or less, and the Fourier coefficients will be scaled by the duty cycle. So while you might look at the clocked output and see a 1Vp sine wave, the fundamental Fourier coefficient would be less than 0.5V. Thus, the gain is actually less that 0.5.

The basic problem stems from the fact that designers are thinking of the switched-capacitor circuit as a discrete-time circuit, and so discount the behavior in between the sample points. By default SpectreRF operates on continuous time signals and so considers the whole signal.

To get the results you expect, you will need to perform a sampling operation on the output. SpectreRF provides this sampling as one of its options.

This situation is described more fully in http://www.designers-guide.org/Analysis/sc-filters.pdf.

-Ken

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jupiter28

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Re: Running Switched-Capacitors simulation
Reply #9 - Oct 11^th, 2011, 8:35am

Hi Ken,

When you mentioned "SpectreRF provides this sampling as one of its options", which option in ADE are you referring to ? Can you be a bit more specific here ?

I am also seeing a similar problem in that the DC gain from PAC (loop gain magnitude plot) is much smaller than my expected DC gain.

I ran PSS and PAC (or PSTB) on my closed-loop system, consisting of a pwm switching converter with a digital filter in the feedback loop. In order to avoid getting "hidden state" errors, i replaced all the "behavioral" registers in my digital filter (modeled in Verilog-A) with your track-and-hold model.

My PSS run converges and transient response looks okay. Basically, the output settles to the correct steady state. Then, i ran PAC and noticed that the DC gain is lowered and the low-frequency dominant pole (from my digital filter) seems to be shifted to the right.

In fact, there are 2 loops in my closed-loop system, i.e. an outer loop formed by the pwm switching converter and digital feedback control and an inner loop within the digital IIR filter. I inserted a vsource (dc=0 pacmag=1) in the outer loop as an ac stimulus.

Can SpectreRF PAC handle this kind of dual loop scenario ?

Please advise.

-albert

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Ken Kundert

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Re: Running Switched-Capacitors simulation
Reply #10 - Oct 11^th, 2011, 9:37pm

Albert,
I don't remember the sampling options. Look around in the PAC options, it has got to be there.

On the rest of your questions, you should not change the subject of a thread. Go back to your original thread and ask the questions there. If you are not getting questions, it is probably because there is too much uncertainty in your question.

-Ken

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