huber
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GO BEARS!
Posts: 45
Los Angeles
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Hello all- I have written a two-phase clock generator in Verilog-A that generates clock waveforms with continuous derivatives. As I understand it, a discontinuous derivative causes spectre to revert to less accurate integration methods, which can cause problems in high resolution ADC simulations. I am using the function y(x) = tanh(x) - x*(1-tanh(3)) for the transition, which has zero derivative at x=-3 and x=3. Unfortunately, x is a hidden state, so the cell is incompatible with spectreRF. I have other hidden states too since I keep track of input clock edges. Anyone have any ideas on how to eliminate the hidden state? Is there a better way to approach the problem? I would like to have the clock frequency defined by a sinewave input. I tried to post the module but apparently it's too long. Still, any help is appreciated. -Dan
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