ASCI/SoC Documentation - Controlling Device Costs

Opportunities

A methodology for the offset-simulation of comparators (140K)

Pattern Generator Model for Jitter-Tolerance Simulation (720 KB)

Orignal Verilog-AMS Paramset proposal (200K)

Engineering Calculator

Upgraded Forum

A Substrate Modeling Methodology

RF Simulation Challenges (paper (130K), presentation (270K))

Experts of The Designer's Guide Community

Modeling RF systems (580 KB)

Comparator metastability analysis (400k)

Principles of top-down mixed-signal design (340 KB)

Why SPICE won't cut it for analog anymore (70 kB)

Moved Designer's Guide Community from www.designers-guide.com to www.designers-guide.org.

Verilog-AMS LRM (version 2.2) (1.9 MB) compressed version (830 KB)

Added power electronics section to Forum.

The Life of Spice by Larry Nagel (70 kB).

The role of high-speed serial interfaces in MS-SoCs (160 kb)

The Designer's Guide to High-Purity Oscillators

The Designer's Guide Bookshelf

An oscillator puzzle, an experiment in community authoring (220 KB)

Expanded library of models on Verilog-AMS.com

SP: Surface-potential-based compact MOSFET model

The Designer's Guide to Verilog-AMS

Recommended Spectre Monte Carlo modeling methodology (123KB)

Verilog-AMS.com

Verilog-AMS LRM (language reference manual) (2.1 MB) compressed version (1 MB)

Simulating the phase noise contribution of the divider in a phase lock loop (75 KB)

Verilog-A LRM (language reference manual) (325 KB) - deleted

Device noise simulation of delta-sigma modulators (1.24 MB)

Predicting the phase noise and jitter of PLL-based frequency synthesizers (updated) (514 KB)

Predicting the phase noise of PLL-based frequency synthesizers (updated) (259 KB)

Modeling jitter in PLL-based frequency synthesizers (updated) (260 KB)

Simulating switched-capacitor filters with SpectreRF (386KB)

Hidden state in SpectreRF (108 KB); Verilog-A models (5 KB)

Modeling diffusion resistors (91KB)

The Designer's Guide Forum

Predicting the phase noise and jitter of PLL-based frequency synthesizers (544 KB)

Predicting the phase noise of PLL-based frequency synthesizers (259 KB)

Modeling jitter in PLL-based frequency synthesizers (260 KB)

VBIC bipolar transistor model

Call for papers

Modeling varactors (updated)

Automatic model compilation, an idea whose time has come

A test bench for differential circuits

Accurate and rapid measurement of IP2 and IP3

A formal top-down design process for mixed-signal circuits

Design of mixed-signal systems on chip

Modeling varactors

Modeling dielectric absorption in capacitors

Noise in mixers, oscillators, samplers, and logic: an introduction to cyclostationary noise (manuscript or presentation)

Modeling and simulation of jitter in PLL frequency synthesizers (removed, inquire if needed)