---------------------------------------------------------------------
-- Block Name: 			FC_JTOL_SRC_NS
-- File Name:			fc_jtol_src_ns.vhd
-- Author:				Paul Muller
-- Date:				18.07.06
-- Rev:				1.0
---------------------------------------------------------------------
-- Modification History (rev, date, author):
-- 1.0, 18.07.06, PMr
-- Official release for DG web site
---------------------------------------------------------------------
-- Please post any questions to
-- http://www.designers-guide.org/Forum
---------------------------------------------------------------------

-------------------------------------------------------------------------------
-- Entity Declarations
-------------------------------------------------------------------------------

library IEEE;
use IEEE.MATH_REAL.all;
library IEEE_PROPOSED;
use IEEE_PROPOSED.electrical_systems.all;
entity sj_src is
	port (
		sj_freq : in real;
		sj_amp : in real;
		freq : in real;
		terminal sj_out : electrical);
end sj_src;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.MATH_REAL.all;
library IEEE_PROPOSED;
use IEEE_PROPOSED.electrical_systems.all;
library LIB_AMS;
use LIB_AMS.all;
entity dj_src is
	port (
		udj_amp : in real;
		nreset : in std_logic;
		terminal dj_out : electrical);
end dj_src;

library IEEE;
use IEEE.MATH_REAL.all;
library IEEE_PROPOSED;
use IEEE_PROPOSED.electrical_systems.all;
library LIB_PCK;
use LIB_PCK.general.all;
entity rj_src is
	port (
		rj_amp : in real;
		terminal rj_out : electrical);
end rj_src;

library IEEE;
use IEEE.MATH_REAL.all;
library IEEE_PROPOSED;
use IEEE_PROPOSED.electrical_systems.all;
library LIB_AMS;
use LIB_AMS.all;
entity sin_clk_src is
	port (
		freq : in real;
		terminal mod_in : electrical;
		terminal sin_clk : electrical);
end sin_clk_src;

library IEEE;
use IEEE.std_logic_1164.all;
library IEEE_PROPOSED;
use IEEE_PROPOSED.electrical_systems.all;
library LIB_AMS;
use LIB_AMS.all;
entity clk_gen is
	port (
		freq : in real;
		sj_amp : in real;						-- Peak-peak value
		sj_freq : in real;
		udj_amp : in real;						-- Peak-peak value
		nreset : in std_logic;
		terminal sin_clk : electrical);
end clk_gen;

library IEEE;
use IEEE.std_logic_1164.all;
entity cjtpat_core is
  port (
    clk : in std_logic;
    rst_b : in std_logic;
    data_out : out std_logic);
end cjtpat_core;

library IEEE;
use IEEE.std_logic_1164.all;
library IEEE_PROPOSED;
use IEEE_PROPOSED.electrical_systems.all;
library LIB_AMS;
use LIB_AMS.all;
entity cjtpat_gen is
	port (
		nreset : in std_logic;
		terminal clk_in : electrical;
		cjtpat : out std_logic);
end cjtpat_gen;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.MATH_REAL.all;
library IEEE_PROPOSED;
use IEEE_PROPOSED.electrical_systems.all;
library LIB_AMS;
use LIB_AMS.all;
entity fc_jtol_src_ns is
	generic (
		data_amp : real := 1.8;						-- data amplitude peak-peak
		data_vcm : real := 0.9);						-- common-mode voltage
	port (
		freq : in real;
		sj_amp : in real;						-- Peak-peak value
		sj_freq : in real;
		rj_amp : in real;						-- RMS value
		udj_amp : in real;						-- Peak-peak value
		ddj_fc : in real;
		nreset : in std_logic;
		terminal data_outp, data_outn : electrical);
end fc_jtol_src_ns;

-------------------------------------------------------------------------------
-- Architecture Declarations
-------------------------------------------------------------------------------


architecture bhv of sj_src is
	constant sj_tau : time := 10ps;
	quantity vsj_out across isj_out through sj_out;
	quantity vsj_int : voltage;
begin
	-- All quantities considered in a 50 Ohm environment
	-- Voltage source is 2 * effective voltage
	-- sj_amp is considered a PP voltage
	-- output signal is centered around Vdd/2=0.0V
	vsj_int == 2.0 * (0.0 + 0.9 * 0.5 * sj_amp * sin(MATH_2_PI*sj_freq*freq*NOW));
	vsj_out == vsj_int + isj_out * 50.0;
end bhv;

architecture bhv of dj_src is
	constant rt, ft : real := 20.0e-12;
	constant num : real_vector := (0 => MATH_2_PI * 50.0e6);
	constant den : real_vector := (0 => MATH_2_PI * 50.0e6,
								1 => 1.0);
	signal sck, sena : std_ulogic := '0';
	signal sdata : std_ulogic := '0';
	signal dj_prbs_real : real := 0.0;
	signal dj_clk, dj_prbs : std_logic := '0';
	quantity dj_out_quant : voltage := 0.0;
	quantity vdj_int : voltage := 1.8;
	quantity vdj_out across idj_out through dj_out;
begin
	-- purpose: Generates Clock for DJ PRBS Gen
	-- type	 : combinational
	-- inputs : dj_clk
	-- outputs: dj_clk
	gen_dj_clk: process (dj_clk)
	begin -- process gen_dj_clk
		dj_clk <= not dj_clk after 0.5 ns;
	end process gen_dj_clk;

	-- DJ PRBS Generator
	gen_dj_prbs : entity LIB_AMS.prbs7(dig)
		port map (
			clk			=> dj_clk,
			sck			=> sck,
			sena			=> sena,
			rst_b			=> nreset,
			sdata		 	=> sdata,
			data_out			=> dj_prbs);

	-- purpose: D2A Conversion for DJ stimulus
	-- type	 : combinational
	-- inputs : dj_prbs
	-- outputs: dj_prbs_real
	dj_prbs_d2a: process (dj_prbs)
	begin -- process dj_prbs_d2a
		if dj_prbs = '0' then
			-- division by 2 as udj_amp is a PP value
			-- multiplication factor to compensate for loss of
			-- amplitude due to incomplete settling
			-- PRBS7 at 1.0 Gb/s has 2.2tau when filtered with
			-- fc = 50MHz (was 1.0587, the 1.0877)
			dj_prbs_real <= 0.0 - 0.9 * udj_amp / 2.0 * 1.1667;
		else
			dj_prbs_real <= 0.0 + 0.9 * udj_amp / 2.0 * 1.1667;
		end if;		
	end process dj_prbs_d2a;
	dj_out_quant == dj_prbs_real'ramp(rt, ft);
	-- All quantities considered in a 50 Ohm environment
	-- Voltage source is 2 * effective voltage
	vdj_int == 2.0 * dj_out_quant'ltf(num, den);
	vdj_out == vdj_int + idj_out * 50.0;	
end bhv;

architecture bhv of rj_src is
	constant rj_tau : time := 10ps;
	signal rj_out_sig : real := 0.0;
	signal mean : real := 0.0;
	signal sigma : real := 0.0;
	quantity vrj_out across irj_out through rj_out;
	quantity vrj_int : voltage;
begin
	-- purpose: Gaussian White Noise Generator
	-- type	 : combinational
	-- inputs : 
	-- outputs: rj_out
	gen_rj: process
		variable seed1 : positive := 19824;
		variable seed2 : positive := 184;
		variable x : real := 0.0;
	begin -- process gen_agwn
		sigma <= 2.0 * 1.8 * MATH_PI * rj_amp;		-- Baumer, "XAUI Jit Specs"
		awgn(seed1, seed2, mean, sigma, x);
		rj_out_sig <= x;
		wait for rj_tau;
	end process gen_rj;	
	-- All quantities considered in a 50 Ohm environment
	-- Voltage source is 2 * effective voltage
	vrj_int == 2.0 * rj_out_sig;
	vrj_out == vrj_int + irj_out * 50.0;		
end bhv;

architecture bhv of sin_clk_src is
	constant kvco : real := 1.5;
	constant PI_OVER_2 : real := MATH_2_PI / 4.0;	-- test
	quantity vsin_clk across isin_clk through sin_clk;
	quantity vmod_in across imod_in through mod_in;
	quantity dph : real;
	quantity inst_ph : real := 1.0;
	quantity vsin_clk_int : voltage;
begin
	-- All quantities considered in a 50 Ohm environment
	-- Voltage source is 2 * effective voltage
	vmod_in == imod_in * 50.0;
	-- Voltage is centered around 0.0V and scaled to full - scale
	dph == vmod_in * kvco * MATH_2_PI / 0.9;
	vsin_clk_int == 2.0 * (0.0 + 0.9 * sin(MATH_2_PI*freq*NOW+dph));
	vsin_clk == vsin_clk_int + isin_clk * 50.0;
end bhv;

architecture str of clk_gen is
	terminal mod_in : electrical;
begin
	i_sj_src: entity LIB_AMS.sj_src(bhv)
		port map (
			sj_amp 			=> sj_amp,
			sj_freq 			=> sj_freq,
			freq	 		=> freq,
			sj_out 			=> mod_in);

	i_dj_src: entity LIB_AMS.dj_src(bhv)
		port map (
			udj_amp 			=> udj_amp,
			nreset 			=> nreset,
			dj_out 			=> mod_in);

	i_sin_clk_src: entity LIB_AMS.sin_clk_src(bhv)
		port map (
			freq 			=> freq,
			mod_in 			=> mod_in,
			sin_clk 				=> sin_clk);		 
end str;

architecture dig of cjtpat_core is
  constant d30p3_pat : std_logic_vector(19 downto 0) :=
	"10000111000111100011";
  constant d21p5_pat : std_logic_vector(19 downto 0) :=
	"10101010101010101010";
  signal counter : natural := 100;
begin
  
  gen_proc : process (clk, rst_b)
  begin
    if rst_b = '0' then
      data_out <= '0';
    elsif clk'EVENT and clk='1' then
      if counter < 100 then 
        data_out <= d30p3_pat(counter mod 20);
      else
        data_out <= d21p5_pat(counter mod 20);
      end if;
      if counter = 130 then
        counter <= 0;
      else     
        counter <= counter + 1;
      end if;
    end if;
  end process gen_proc;
end dig;

architecture bhv_str of cjtpat_gen is
	constant clk_thresh1 : real := -0.05;
	constant clk_thresh2 : real :=	0.05;
	signal sq_clk : std_logic := '0';
	quantity vclk_in across iclk_in through clk_in;
begin
	vclk_in == iclk_in * 50.0;
	
	-- purpose: Detects zero crossings of the reference clock
	-- type	 : combinational
	-- inputs : sin_jit_clk
	-- outputs: sq_jit_clk
	edge_det_clk: process (vclk_in'above(clk_thresh1),
	vclk_in'above(clk_thresh2))
	begin -- process edge_det_clk
		if not vclk_in'above(clk_thresh1) then
			sq_clk <= '0';
		elsif vclk_in'above(clk_thresh2) then
			sq_clk <= '1';
		end if;
	end process edge_det_clk;

	-- CJTPAT Generator
	gen_cjtpat : entity LIB_AMS.cjtpat_core(dig)
		port map (
			clk			=> sq_clk,
			rst_b		 	=> nreset,
			data_out			=> cjtpat);
end bhv_str;

architecture bhv of fc_jtol_src_ns is
	constant rt, ft : real := 20.0e-12;
	terminal clk_in : electrical;
	signal cjtpat : std_logic := '0';
	signal cjtpat_real : real := 0.0;
	quantity cjtpat_quant : voltage;
	quantity vdata_out across idata_out through data_outp to data_outn;
begin

	i_clk_gen : entity LIB_AMS.clk_gen(str)
		port map (
			sj_freq 			=> sj_freq,
			sj_amp			=> sj_amp,
			udj_amp			=> udj_amp,
			freq			=> freq,
			nreset			=> nreset,
			sin_clk 			=> clk_in);

	i_rj_src : entity LIB_AMS.rj_src(bhv)
		port map (
			rj_amp 			=> rj_amp,
			rj_out 			=> clk_in);

	i_cjtpat_gen : entity LIB_AMS.cjtpat_gen(bhv_str)
		port map (
			nreset		 	=> nreset,
			clk_in		 	=> clk_in,
			cjtpat		 	=> cjtpat);

	cjtpat_d2a: process (cjtpat)
	begin
		if cjtpat = '0' then
			cjtpat_real <= data_vcm - data_amp / 2.0;
		else
			cjtpat_real <= data_vcm + data_amp / 2.0;
		end if;		
	end process cjtpat_d2a;
	cjtpat_quant == cjtpat_real'ramp(rt, ft);
	vdata_out'dot / (MATH_2_PI * ddj_fc) + vdata_out == cjtpat_quant;
end bhv;

---------------------------------------------------------------------
-- Block Name: 	General Functions Package
-- File Name:	general.vhd
-- Author:	Paul Muller
-- Date:	16.07.04
-- Rev:		1.0
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.math_real.all;

package general is

	procedure awgn (
		variable seed1, seed2 : inout positive;
		signal	 mean, sigma : in real;
		variable x : out real);

end general;

package body general is
procedure awgn (
		variable seed1, seed2 : inout positive;
		signal	 mean, sigma : in real;
		variable x : out real
		) is
		variable r1, r2 : real:= 0.0;
	begin
		UNIFORM(seed1, seed2, r1);
		UNIFORM(seed1, seed2, r2);
		x := mean + sigma * (sqrt( -2.0 * log( r1 )) * cos( 2.0 * MATH_PI * r2 ));
	end procedure awgn;
end general;