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Verilog-A model extraction in ICCAP for Spectre (Read 70 times)
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Verilog-A model extraction in ICCAP for Spectre
Jan 29th, 2019, 4:45pm
I am extracting Verilog-A based model with ICCAP for spectre simulator.
This Verilog-a model is not within/built in Spectre simulator. So, the simulator is reading the Verilog-a model from my local directory.
Previously, when I have extracted other models like BSIM or PSP, those seem to much faster in terms of simulation time for extracting the model as the model were built in within the simulator.

Do, mmsim need to compile the verilog-a code each time it run the simulation or I can disable each running of the spectre.

Not sure, If I had explained it in details.

Thanks in advance.

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« Last Edit: Jan 29th, 2019, 6:04pm by Ziauddin »  
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Re: Verilog-A model extraction in ICCAP for Spectre
Reply #1 - Jan 31st, 2019, 7:12am
Generally, I think ICCAP is slower when it has to call out to an external simulator, compared to running the simulation internally. ICCAP does have Verilog-A capability, but I don't know if it needs an extra license (it did some years ago).
Most simulators that support Verilog-A do cache the compiled object. However, if the .va file is in a directory where you don't have write access, then the simulator may have trouble finding the compiled object from a previous run. You should try running Spectre outside of ICCAP and see whether it is able to re-use the compiled object, and/or look at the Spectre log file for the ICCAP simulations, which should report whether it is re-compiling the model or loading a pre-compiled object.
Also, you may want to reach out to Cadence to see if they have any suggestions for speeding up the simulation of Verilog-A compact models.
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