The Designer's Guide Community
Forum
Models in Minutes
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines. Dec 15th, 2018, 11:51pm
  HomeHelpSearchLoginRegisterPM to admin  
 
Pages: 1
Send Topic Print
Verilog-A : Behavioral model analyzer/optimizer (Read 66 times)
AS
Junior Member
**
Offline



Posts: 18
US
Verilog-A : Behavioral model analyzer/optimizer
Dec 05th, 2018, 4:38pm
 
Hello All,

Is there an analyzer mode in any spice simulator that can help with identification of
simulation speed bottlenecks in Verilog-A models?

Thanks,
AS
Back to top
 
 
View Profile   IP Logged
Frank Wiedmann
Community Fellow
*****
Offline



Posts: 642
Munich, Germany
Re: Verilog-A : Behavioral model analyzer/optimizer
Reply #1 - Dec 7th, 2018, 2:06am
 
Back to top
 
 
View Profile WWW   IP Logged
Andrew Beckett
Senior Fellow
******
Offline

Life, don't talk to
me about Life...

Posts: 1693
Bracknell, UK
Re: Verilog-A : Behavioral model analyzer/optimizer
Reply #2 - Dec 7th, 2018, 4:28am
 
Spectre has an "AHDL Linter". This can be turned on in ADE via Simulation->Options->Analog and is on the Miscellaneous tab. From the command line it's the -ahdllint option.

There are some static checks which will then appear in the normal simulator output log, and then some checks during simulation for potential performance issues or improvements (in ADE the Linter log can be shown from the Simulation menu).

Regards,

Andrew.
Back to top
 
 
View Profile WWW   IP Logged
Pages: 1
Send Topic Print
Trouble viewing this site? Copyright © 2002-2018 Designer's Guide Consulting. 'Designer's Guide' is a registered trademark of Designer's Guide LLC. All rights reserved.

Our colleges are not as safe as they seem. Sexual assault is pervasive and the treatment of the victim by the adminstration is often as damaging as the assault: Campus Survivors, Campus Survivors Forum.

Some of our other sites that you might find useful: Avendesora, Inform and QuantiPhy.