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non-overlapping clock issue in a SC delta sigma modulator (Read 64 times)
polyam
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non-overlapping clock issue in a SC delta sigma modulator
Sep 08th, 2018, 5:21pm
 
Hi,

I've designed a 2nd order SC delta-sigma modulator to support 10kHz signal bandwidth. The OSR is 256 resulting in a 5.12MHz oversampling frequency. The OTAs used for the integrators are overdesigned to properly settle down even for a 20-MHz oversampling frequency. Just giving some numbers (DC-gain=120dB, UGBW=220MHz, phase margin=64). all switches and quantizer are transistorized.

The fully transistorized modulator perfectly works with a sampling frequency of 5MHz when I apply an IDEAL non-overlapping clock signal. The modulator works also well when I increase the clock frequency to 20 MHz and integrating the noise over 40kHz (OSR still 246) again with an IDEAL non-overlapping clock frequency.

Now here is the problem!!
I replaced the ideal non-overlapping clock signal with a transistorized one. The modulator works well when the master clock is 5.12 MHz. BUT when I increase the master clock to 20MHz, I see a severe SNDR degradation.


Does anyone have any idea to fix this issue? What causes this issue?
(I'll post spectrum in different cases)

Thanks







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polyam
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Re: non-overlapping clock issue in a SC delta sigma modulator
Reply #1 - Sep 8th, 2018, 5:24pm
 
When I use an ideal 20MHz non-overlapping clock and BW is 40kHz. The modulator works.
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Ideal_clk_20MHz.png
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polyam
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Re: non-overlapping clock issue in a SC delta sigma modulator
Reply #2 - Sep 8th, 2018, 5:25pm
 
When I use a transistorized non-overlapping clock signal. Master clock is 5.12MHz and BW is 10 kHz.
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real_clk_5MHz.png
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polyam
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Re: non-overlapping clock issue in a SC delta sigma modulator
Reply #3 - Sep 8th, 2018, 5:26pm
 
When I use a transistorized non-overlapping clock signal. Master clock is 20 MHz over a BW of 40kHz.
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real_clk_20MHz.png
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polyam
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Re: non-overlapping clock issue in a SC delta sigma modulator
Reply #4 - Sep 8th, 2018, 5:30pm
 
From my third spectrum, it's kind of weird. It looks like that I have a delay probably in the feedback path. The shape of the spectrum over fs/2 makes me conclude that! But anyway, I didn't change anything in the modulator. Just changing the master clock to 20 MHz and that's it!
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