Hi everyone,

when i look at the layout of the pcell ,there is space between the last contact on one terminal and edge of diffusion, but when i load that instance in layout , the last contact is appearing at the edge of diffusion, DRC is giving a min space error.
i checked for NMOS and PMOS, layout is same as pcell. Did anyone face this issue before ?
i uploaded the pic below.

Regards
Abhilash