The Designer's Guide Community
Models in Minutes
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines. Dec 14th, 2018, 11:55pm
  HomeHelpSearchLoginRegisterPM to admin  
Pages: 1
Send Topic Print
Help with a verilog-A code (Read 422 times)
New Member

Posts: 1

Help with a verilog-A code
Jul 31st, 2018, 3:54am

I am trying to create a verilog-A model consisting of many switches, one end of all of them being connected to a source, and the other end available as a pin. It is required that the switches turn on in sequence after fixed time intervals, with only one switch being on at a time. For this, I have tried something like this.

module X(capout,gnd);
vsource #(<some source>) vin(out_temp,gnd);
genvar j,x;
analog begin
  @(initial_step or initial_step("dc", "ac", "tran", "xf")) begin
  generate i (0, 2) begin
  ival[i] = 0 ;
  for ( j = 0 ; j<=2 ; j = j +1 ) begin
    @(timer(0,40u)) begin
    V(capout[j]) <+ V(out_temp);
    for (x=0; x<=2; x=x+1)  begin
      if (x!=j) begin
        ival[x] = 0;
    generate i (0,2) begin
    I(capout[i]) <+ ival[i];

On running this, however, I get the following error.
Error found by spectre during AHDL read-in.
   ERROR (VACOMP-2157): "../", line 24: Encountered a contribution statement embedded in an analog event. Remove the contribution statement from the analog event

It seems that the simulator isn't able to assign the voltage to 'capout[j]' for time steps other than the ones when the timer event occurs. In those times, it is required to float the pin. It is for this very purpose that I have assigned the current function a zero value for all other pins.
Is there any way out to resolve this issue?

Back to top
View Profile   IP Logged
Ken Kundert
Global Moderator

The Spectre

Posts: 2133
Silicon Valley
Re: Help with a verilog-A code
Reply #1 - Jul 31st, 2018, 11:23am
Your code is written such that the switch is closed only at the instant of time when the timer function fires. That is what the simulator is complaining about. Probably what you want is something like the following:

module mux (a, c);
electrical [2:0] a;
electrical c;
integer i;
analog begin
    @(timer(0, 40u)) i = (i + 1) % 4;
    I(a[0], c) <+ transition(i == 0, 0, 1u) * V(a[0], c);
    I(a[1], c) <+ transition(i == 1, 0, 1u) * V(a[1], c);
    I(a[2], c) <+ transition(i == 2, 0, 1u) * V(a[2], c);
    I(a[3], c) <+ transition(i == 3, 0, 1u) * V(a[3], c);

If your mux is connected to capacitors, you will probably need to add gmin to each a input to prevent floating nodes.

Back to top
View Profile WWW   IP Logged
Pages: 1
Send Topic Print
Trouble viewing this site? Copyright © 2002-2018 Designer's Guide Consulting. 'Designer's Guide' is a registered trademark of Designer's Guide LLC. All rights reserved.

Our colleges are not as safe as they seem. Sexual assault is pervasive and the treatment of the victim by the adminstration is often as damaging as the assault: Campus Survivors, Campus Survivors Forum.

Some of our other sites that you might find useful: Avendesora, Inform and QuantiPhy.