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veriloga counter_ (Read 488 times)
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veriloga counter_
Jul 06th, 2018, 9:34am
i have to implement a counter in verilog-A that counts the number of beats of a signal(beat frequency counter). for example, the input pulse is varying (5u s, 12u s , 14u s) and the reference signal is 1u s. i want the counter to to give (5 , 12 , 14). in decimal or in analog format.

The verilog-A im writing is as follows:
module counter_a(vout, vclk, vin);

input vclk, vin;
electrical vout,  vclk, vin;
parameter real vlogic_high = 1.0;
parameter real vlogic_low = 0;
parameter real vtrans_clk = 0.6;
parameter real vtrans = 0.6;
parameter real tdel = 50p from [0:inf);
parameter real trise = 20p from (0:inf);
parameter real tfall = 20p from (0:inf);

real x;

  analog begin
     @ (cross( V(vin) - vtrans_clk, +1 ))
           V(x) = ( V(vin) * V(vclk));


           V(vout) <+ transition ( V(x) * vlogic_high, tdel, trise, tfall);

//      $strobe ("Count is %d", x);


please any help
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Ken Kundert
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The Spectre

Posts: 2145
Silicon Valley
Re: veriloga counter_
Reply #1 - Jul 7th, 2018, 1:15am
Your model exhibits several obvious problems, but fixing them would not result in the counter you are looking for.

Perhaps you could explain the basic algorithm of what you are trying to accomplish.

Also, when including code, you should use the code markup (push the button marked with a #). It makes the code easier to read.

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