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Hierarchical net reference question (Read 312 times)
SteveRosenbaum
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Hierarchical net reference question
Jun 03rd, 2018, 10:52am
 
Hi all,

I am trying to reference an indexed net (like a multi numbered net) in hierarchy.  Let me explain:

If the net was regular, non-indexed:

V ( Level2.Level1.Level0.net_name ) <+ 5;

That works fine.  But if the net has an index, which Virtuoso puts in angle brackets (i.e. net_name<3:0>)

V (Level2.Level1.Level0.net_name<2> ) <+ 5;

Does NOT work.  I can't change to square brackets, because then the net is not recognized in the circuit.

Does anyone have a suggestion.  Sorry if this has been answered before.  I haven't been able to find the answer after many searches.

Thanks,
Steve
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Ken Kundert
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Re: Hierarchical net reference question
Reply #1 - Jun 4th, 2018, 2:09am
 
The angle brackets are a convention used in the design environment that is not shared with the simulator. They are always converted to square brackets when sending the design to the simulator. The simulator always uses square brackets. So I don't think your explanation is correct. I suspect there is something else going wrong. I would not at all be surprised that electrical arrays were not supported as hierarchical references, but I have never tried it, so I don't know. I do know that Cadences simulator imposes several limitations on electrical arrays.

Perhaps you should show us the error message (always a good idea when asking for help as there is always the possibility that you are misinterpreting it).

-Ken
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SteveRosenbaum
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Re: Hierarchical net reference question
Reply #2 - Jun 5th, 2018, 11:06am
 
Thanks, Ken.  Now that I know it should have recognized the square brackets I'll try again and pay closer attention to the error message.  I think that because I wasn't sure if square brackets would work, I just figured that it was the problem.
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SteveRosenbaum
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Re: Hierarchical net reference question
Reply #3 - Jun 6th, 2018, 2:25pm
 
OK - I tried again to replace with square brackets and it still doesn't work.  Is the problem that I'm using Verilog-A and Spectre simulation (NOT AMS)?  I have a feeling that's it.

If the problem is that it's a Spectre Sim with Verilog-A, is there a different way to reference these nets?  

Here are the errors from the sim log:

Error found by spectre during hierarchy flattening.
   ERROR (SFE-3251): Out-of-module reference node `I_TOP.I_CORE.isns_comp_en[0]' in Verilog-A instance `AnalogStimulus' does not exist in design.
   ERROR (SFE-3251): Out-of-module reference node `I_TOP.I_CORE.isns_comp_en[1]' in Verilog-A instance `AnalogStimulus' does not exist in design.
   ERROR (SFE-3251): Out-of-module reference node `I_TOP.I_CORE.vac_adc_comp_en[0]' in Verilog-A instance `AnalogStimulus' does not exist in design.
   ERROR (SFE-3251): Out-of-module reference node `I_TOP.I_CORE.vac_adc_comp_en[1]' in Verilog-A instance `AnalogStimulus' does not exist in design.
   ERROR (SFE-3251): Out-of-module reference node `I_TOP.I_CORE.vbus_adc_comp_en[0]' in Verilog-A instance `AnalogStimulus' does not exist in design.
   ERROR (SFE-3251): Out-of-module reference node `I_TOP.I_CORE.vbus_adc_comp_en[1]' in Verilog-A instance `AnalogStimulus' does not exist in design.
   ERROR (SFE-3251): Out-of-module reference node `I_TOP.I_CORE.vbus_adc_comp_en[2]' in Verilog-A instance `AnalogStimulus' does not exist in design.
   ERROR (SFE-3251): Out-of-module reference node `I_TOP.I_CORE.vbus_adc_comp_en[3]' in Verilog-A instance `AnalogStimulus' does not exist in design.
   ERROR (SFE-3251): Out-of-module reference node `I_TOP.I_CORE.vbus_adc_comp_en[4]' in Verilog-A instance `AnalogStimulus' does not exist in design.
   ERROR (SFE-3251): Out-of-module reference node `I_TOP.I_CORE.vbus_adc_comp_en[5]' in Verilog-A instance `AnalogStimulus' does not exist in design.
   ERROR (SFE-3251): Out-of-module reference node `I_TOP.I_CORE.vbus_adc_comp_en[6]' in Verilog-A instance `AnalogStimulus' does not exist in design.
   ERROR (SFE-3251): Out-of-module reference node `I_TOP.I_CORE.GPIO0_SEL[2]' in Verilog-A instance `AnalogStimulus' does not exist in design.
   ERROR (SFE-3251): Out-of-module reference node `I_TOP.I_CORE.GPIO0_SEL[1]' in Verilog-A instance `AnalogStimulus' does not exist in design.
   ERROR (SFE-3251): Out-of-module reference node `I_TOP.I_CORE.GPIO0_SEL[0]' in Verilog-A instance `AnalogStimulus' does not exist in design.
   ERROR (SFE-3251): Out-of-module reference node `I_TOP.I_CORE.GPIO1_SEL[2]' in Verilog-A instance `AnalogStimulus' does not exist in design.
   ERROR (SFE-3251): Out-of-module reference node `I_TOP.I_CORE.GPIO1_SEL[1]' in Verilog-A instance `AnalogStimulus' does not exist in design.
   ERROR (SFE-3251): Out-of-module reference node `I_TOP.I_CORE.GPIO1_SEL[0]' in Verilog-A instance `AnalogStimulus' does not exist in design.
   ERROR (SFE-3251): Out-of-module reference node `I_TOP.I_CORE.GPIO2_SEL[2]' in Verilog-A instance `AnalogStimulus' does not exist in design.
   ERROR (SFE-3251): Out-of-module reference node `I_TOP.I_CORE.GPIO2_SEL[1]' in Verilog-A instance `AnalogStimulus' does not exist in design.
   ERROR (SFE-3251): Out-of-module reference node `I_TOP.I_CORE.GPIO2_SEL[0]' in Verilog-A instance `AnalogStimulus' does not exist in design.
   ERROR (SFE-3251): Out-of-module reference node `I_TOP.I_CORE.GPIO3_SEL[2]' in Verilog-A instance `AnalogStimulus' does not exist in design.
   ERROR (SFE-3251): Out-of-module reference node `I_TOP.I_CORE.GPIO3_SEL[1]' in Verilog-A instance `AnalogStimulus' does not exist in design.
   ERROR (SFE-3251): Out-of-module reference node `I_TOP.I_CORE.GPIO3_SEL[0]' in Verilog-A instance `AnalogStimulus' does not exist in design.
   ERROR (SFE-3251): Out-of-module reference node `I_TOP.I_CORE.GPIO0_ATS[1]' in Verilog-A instance `AnalogStimulus' does not exist in design.
   ERROR (SFE-3251): Out-of-module reference node `I_TOP.I_CORE.GPIO0_ATS[0]' in Verilog-A instance `AnalogStimulus' does not exist in design.
   ERROR (SFE-3251): Out-of-module reference node `I_TOP.I_CORE.GPIO1_ATS[1]' in Verilog-A instance `AnalogStimulus' does not exist in design.
   ERROR (SFE-3251): Out-of-module reference node `I_TOP.I_CORE.GPIO1_ATS[0]' in Verilog-A instance `AnalogStimulus' does not exist in design.
   ERROR (SFE-3251): Out-of-module reference node `I_TOP.I_CORE.GPIO2_ATS[1]' in Verilog-A instance `AnalogStimulus' does not exist in design.
   ERROR (SFE-3251): Out-of-module reference node `I_TOP.I_CORE.GPIO2_ATS[0]' in Verilog-A instance `AnalogStimulus' does not exist in design.
   ERROR (SFE-3251): Out-of-module reference node `I_TOP.I_CORE.GPIO3_ATS[1]' in Verilog-A instance `AnalogStimulus' does not exist in design.
   ERROR (SFE-3251): Out-of-module reference node `I_TOP.I_CORE.GPIO3_ATS[0]' in Verilog-A instance `AnalogStimulus' does not exist in design.

Time for Elaboration: CPU = 1.35379 s, elapsed = 3.37577 s.
Time accumulated: CPU = 1.69074 s, elapsed = 4.196 s.
Peak resident memory used = 109 Mbytes.
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