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Simulation for Injection Locked PLL (Read 498 times)
Junior Member

Posts: 10

Simulation for Injection Locked PLL
Apr 24th, 2018, 2:12pm
I am trying to model the behavior of injection locked bang-bang PLL using verilog-A model for the comparator and the loop filter but with oscillator in spice (schematic view) in virtuoso.
In this simulation I start the PLL and let it lock at the desired frequency and then I enable the injection. But in the simulation results I see that when I enable the injection the frequency of the oscillator goes up from the desired frequency.
I am unable to understand why is this happening, can somebody suggest a possible fix to this problem.
I have attached the snippet of the output frequency of the PLL after its locked before and after injection.
The desired frequency is 2.56GHz but after injection it goes to around 2.561GHz with periodic frequency spurs due to injection.
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Posts: 39
Frankfurt, Germany
Re: Simulation for Injection Locked PLL
Reply #1 - May 3rd, 2018, 2:57am
To have more precise answer I would request you to attach the circuit/block diagram and the input clock frequency. Regarding the undershoots, it can be caused if the injecting signal is lying at the edge of locking range. This leads to quasi locking. You should increase the locking range in this case.
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