I am trying to model the behavior of injection locked bang-bang PLL using verilog-A model for the comparator and the loop filter but with oscillator in spice (schematic view) in virtuoso.
In this simulation I start the PLL and let it lock at the desired frequency and then I enable the injection. But in the simulation results I see that when I enable the injection the frequency of the oscillator goes up from the desired frequency.
I am unable to understand why is this happening, can somebody suggest a possible fix to this problem.
I have attached the snippet of the output frequency of the PLL after its locked before and after injection.
The desired frequency is 2.56GHz but after injection it goes to around 2.561GHz with periodic frequency spurs due to injection.
Thanks!