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glitches of switched-capacitor circuits (Read 609 times)
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glitches of switched-capacitor circuits
Apr 11th, 2018, 5:10am
what are the switched capacitor glitches that can be solved by making a good clock generator.

I have a clock generator made and its application is to test the clocks to a switched capacitor, what are the parameters that i should look for if I'm aiming to solve those glitches using my clock generator.

My clock Generator frequency is 32kHz and another question is what kind of switched capacitor I can use for this?

Im doing my circuit design in TSMC 65 nm technology.

Also if you can provide or tell some full research paper regarding my matter, it would be very helpful.
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Re: glitches of switched-capacitor circuits
Reply #1 - Apr 16th, 2018, 2:13am
I don't understand your questions very well. You need a clock generattor to control the switched-capacitor circuits, right? If so, you want your clock generator is glitch free, right? My question is how do you get your clock signals? You design your RC oscillator or XO to generate a clock or you just use a ideal clock signal directly? If you design your own oscillator, normally the glitch is not a big concern when the oscillator is running smoothly, you need to take care the PSRR.
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Re: glitches of switched-capacitor circuits
Reply #2 - May 15th, 2018, 10:21pm

charge injections of switched capacitor circuits
compensation of charge injected in CMOS switches

That should get you started. This is an old topic that was been around a long time and was originally covered in journal papers back in the 1980's, and is in some of the analog CMOS design texts.
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