In deep sub-micron process, usually LDMOS can be used for higher voltage tolerance.

With drain extension, it is understood that Vds tolerance can be increased.

However, why Vgd tolerance is also increased?

For example, in 40nm process 3.3v oxide, LDMOS Vgd can tolerate 5V?

I don't understand why Vgd (involving oxide) can be increased when there is no current?