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SAR ADC SNDR degradation due to bins around DC (Read 2987 times)
DanielLam
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Re: SAR ADC SNDR degradation due to bins around DC
Reply #15 - Apr 04th, 2018, 9:56pm
 
What switch mechanism is causing the distortion? What is causing this voltage dependence?

Try simplifying the problem. Have you just tried 1 switch + 1 capacitor + ideal ADC, and looking at that FFT? (this should be less than 10 seconds).

Do you see the same distortion?

I agree going to a bootstrap switch will help. But you should know what is causing your main problem. I don't think you fully understand why the switch is behaving this way.
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niloun
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Re: SAR ADC SNDR degradation due to bins around DC
Reply #16 - Apr 5th, 2018, 10:07am
 
DanielLam wrote on Apr 4th, 2018, 9:56pm:
What switch mechanism is causing the distortion? What is causing this voltage dependence?


DanielLam wrote on Apr 4th, 2018, 9:56pm:
I agree going to a bootstrap switch will help. But you should know what is causing your main problem. I don't think you fully understand why the switch is behaving this way.


I have done so many simulations since I read your answer and I have thought a lot about the things that you asked. I am a bit confused because I am trying to come up with a right answer to you but I am not sure if your answer is another solution for the design or you want me to say the cause of the effect that I see.

There are a few things that came to my mind.

You asked : What switch mechanism is causing the distortion? What is causing this voltage dependence?

If you mean the voltage dependence and non-linearity of the switches, it is because of the signal dependent on-resistance of the transistors. There is a big voltage variation of the Vgs of the transistors.

But if you do not accept this answer for the transistors misbehavior and you want more detailed answer, I have a few ideas:

1- the loading effect of the DAC capacitive array on the switches and KT/C noise.
2- The kickback noise of the comparator.
3- Improper sizing of the capacitive DAC.
4- Not using a capacitor between the switch output and ground.

DanielLam wrote on Apr 4th, 2018, 9:56pm:
Try simplifying the problem. Have you just tried 1 switch + 1 capacitor + ideal ADC, and looking at that FFT? (this should be less than 10 seconds).

Do you see the same distortion?


This one is making me more confused. I have done what you said and I got these results:

Switch+ Cap(1pF to ground) + Ideal ADC : ENOB=6.7649 of 8

Switch + Ideal ADC: ENOB=5.4948 of 8


The bins around DC are gone but the one near the sigbin is the 3rd harmonic.

Maybe this capacitor is fixing the output voltage of the switch but I have tried the same in my own design and I didn't see much improvement.

Dismissing the third harmonic we don't see the DAC loading and comparator effects here anymore, so again this could help us understand that the capacitive DAC or the comparator are causing a problem. Comparator Kickback noise or capacitive load.

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DanielLam
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Re: SAR ADC SNDR degradation due to bins around DC
Reply #17 - Apr 5th, 2018, 1:41pm
 
Based on your results, I think you need to just concentrate on the sample and hold action. After that, you can start worrying about comparator problems (which I'm pretty sure is NOT the issue). You are already seeing distortion with a simple switch and capacitor (no ADC effects).

What about switch charge injection? Are you doing bottom plate sampling? Does this help fix your ideal ADC model, and you get back close to the ideal ENOB?

Slide 3 is how a your ADC should be sampling. Two switches in series with the capacitor. The one connected to gnd or vcm should be open'ed first, then the input sampling switch. This will reduce charge injection going into the ADC.
https://inst.eecs.berkeley.edu/~ee247/fa09/files07/lectures/L18_2_f09.pdf

Similar thing on slide 33 of the sample and hold pptx
http://www.utdallas.edu/~yxc101000/courses/7327/handout.html


Note, just for future reference, in faster interleaved ADCS, this technique is not always used due to speed considerations (there are 2 switches in series now instead of 1 for the time constant). But the charge injection is not a major error in these designs.
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niloun
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Re: SAR ADC SNDR degradation due to bins around DC
Reply #18 - Apr 6th, 2018, 11:52am
 
DanielLam wrote on Apr 5th, 2018, 1:41pm:
Based on your results, I think you need to just concentrate on the sample and hold action. After that, you can start worrying about comparator problems (which I'm pretty sure is NOT the issue). You are already seeing distortion with a simple switch and capacitor (no ADC effects).

What about switch charge injection? Are you doing bottom plate sampling? Does this help fix your ideal ADC model, and you get back close to the ideal ENOB?

Slide 3 is how a your ADC should be sampling. Two switches in series with the capacitor. The one connected to gnd or vcm should be open'ed first, then the input sampling switch. This will reduce charge injection going into the ADC.
https://inst.eecs.berkeley.edu/~ee247/fa09/files07/lectures/L18_2_f09.pdf

Similar thing on slide 33 of the sample and hold pptx
http://www.utdallas.edu/~yxc101000/courses/7327/handout.html


Note, just for future reference, in faster interleaved ADCS, this technique is not always used due to speed considerations (there are 2 switches in series now instead of 1 for the time constant). But the charge injection is not a major error in these designs.


I did what you said but unfortunately didn't work (Vcm being opened 200p s earlier).
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DanielLam
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Re: SAR ADC SNDR degradation due to bins around DC
Reply #19 - Apr 6th, 2018, 12:46pm
 
If you do bottom plate sampling, did you also remove the charge cancellation dummy devices?
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niloun
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Re: SAR ADC SNDR degradation due to bins around DC
Reply #20 - Apr 6th, 2018, 1:11pm
 
DanielLam wrote on Apr 6th, 2018, 12:46pm:
If you do bottom plate sampling, did you also remove the charge cancellation dummy devices?


The config that I use is exactly like this:

X is connected to the comparator.
For the Vcm (0.9V) which goes into the comparator I have used a simple complementary switch.

input switches are complementary switches with dummies.

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DanielLam
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Re: SAR ADC SNDR degradation due to bins around DC
Reply #21 - Apr 6th, 2018, 1:36pm
 
Try taking out the dummy cancellation switches. They will actually hurt performance if you use bottom plate sampling (because the charge injection is already cancelled to a first order by the bottom plate sampling).
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niloun
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Re: SAR ADC SNDR degradation due to bins around DC
Reply #22 - Apr 9th, 2018, 6:37am
 
DanielLam wrote on Apr 6th, 2018, 1:36pm:
Try taking out the dummy cancellation switches. They will actually hurt performance if you use bottom plate sampling (because the charge injection is already cancelled to a first order by the bottom plate sampling).


I did a few other things and the problem still exist:

1- Using buffer in the inputs of the comparator.
2- Using simple complementary switches and bottom plate sampling. (I mean  switches without dummies and turning the Vcm off 1n earlier than input voltage switches).
3- I did #2 with two sizing : (30u/10u and 220n/660n)


I read somewhere that this phenomenon could be because of subthreshold leakage current and now I am increasing the length of transistors to see what will happen.
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DanielLam
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Re: SAR ADC SNDR degradation due to bins around DC
Reply #23 - Apr 9th, 2018, 6:24pm
 
I'm guessing it's not the channel length unless you are simulating at 100C+.

What was the difference between the 2 different sized switches? By the way, I think 220n/660n is way too small. I would have probably tried 4um/12um as the smaller size.
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niloun
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Re: SAR ADC SNDR degradation due to bins around DC
Reply #24 - Apr 23rd, 2018, 4:05am
 
Sorry for the delay. In the meantime I did some other things which none of them helped much and I see the same problem with the conventional structure that I designed too.

DanielLam wrote on Apr 9th, 2018, 6:24pm:
I'm guessing it's not the channel length unless you are simulating at 100C+.

What was the difference between the 2 different sized switches? By the way, I think 220n/660n is way too small. I would have probably tried 4um/12um as the smaller size.


for 220n/660n : ENOB=5.3
for 5u/15u : ENOB=5.6

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