I have already read this read and I didn't find any concrete answer
http://www.designers-guide.org/Forum/YaBB.pl?num=1342834861

My question is very similar to this one. I did the Pnoise analysis of a charge sensitive OTA with CDS scheme. From the figure, you can see the suppression of the low-frequency noise ad increased in Thermal noise PSD (sue to noise folding) which is very obvious from the theory.
Ref:http://www.designers-guide.org/analysis/sc-filters.pdf

In the following picture, the Red curve represents the continuous output noise spectrum with CDS caps(simulation is done in the continuous time domain). The blue curve is the output noise spectrum(PSS followed by Pnoise) with CDS caps.

Whats bothering me is the noise in band of 1-10Hz, I don't understand why noise is not flat over there?  In principle, it should be flat because CDS has high pass characteristics and it should also suppress noise in that band (i.e 1-10Hz) .

If you need more information about simulation environment for your answers let me know.

Thanks

It is worth looking at this post on flicker noise in chopper stabilized amplifiers. They were experiencing a similar problem.

Effectively in a CDS you are expecting the flicker noise to be suppressed through cancellation. Your results suggest that you are getting some cancellation, but not complete cancellation. You seem to be getting about 30 dB of cancellation, which seems reasonable.  Why are you expecting anything better than that?

-Ken

In concept, CDS works by sampling the offset and subtracting it off. In your circuit you are getting about 30 dB of cancellation, meaning that your are canceling roughly 97% of the offset. To get rid of the offset completely, the sampling and subtraction must be perfect. For example, you would see the levels of performance you are seeing if the sampled offset were to droop roughly 3% between when the sample was taken and when the correction is applied. Another possible source of error is feed through, a small amount of input signal feeds through the sampler or perhaps directly from the input to the output. In my experience, the capacitance are very small in CDS circuits and impedance levels are high, meaning that small parasitics could create significant feed through.

The situation with choppers is similar but different. With CDS the offsets and low frequency noise are eliminated through a sample and correct process. With choppers is a modulation process. With choppers, the issue is symmetry, the better the symmetry the better the suppression of the offset. Essentially with choppers there are two nearly equal and opposite paths. If the paths are identical yet opposite, then the error suppression will be perfect. In practice you cannot get two identical but opposite paths in the actual circuit, but you conceivably could in a simulation where perfect symmetry is possible. So you might expect that when simulating choppers you could get perfect suppression, but there is another form of asymmetry that you need to be aware of, and that is in the time steps the simulator is taking. For perfect cancellation, the simulator needs to take precisely the same time steps in each half cycle. This is something you don't have a lot of control over. In practice, the timestep asymmetry will prevent you from getting perfect cancellation, but at 30 dB I believe you are well above the simulator imposed accuracy constraints.

-Ken

Each FET has multiple noise sources, each of which acts as an input.

You can ask the simulator for the noise summary, it will tell you which device the noise is coming from. That can help you understand the how the noise is getting to the output.

-Ken