Repah,

   There is no reason why a top level verification should not converge.
I have run similar simulations in the past, see the attached example.
The primary difference appears to be in the switching.  It does look like
you are crowbarring the reference voltages that might be problematic.

Repah,

    There should be no need to set the time step for this simulation.
The appropriate way to control the time step is to let the simulator
set the time step by setting the accuracy control, error preset. Start
with an error preset of moderate. If you need more accuracy try
using the Conservative error preset.

   The reason you might want to set the time step is to force the
simulator to take a time step is to force the time step for the DFT.
It should not be required for this simulation.

                                                           Sheldon