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relation between CMOS technology and speed of I/O (Read 417 times)
aguntuk
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Dresden, Germany
relation between CMOS technology and speed of I/O
Dec 14th, 2017, 3:28pm
 
I have a basic question about the speed of high-speed channel or I/O and the CMOS technology (aka gate technology). In many papers, I read people are designing or optimizing the design of high-speed channel or I/O like 40 Gbps or any data rate in 0.13 um or 65nm CMOS. In these paper, no one says why they choose that CMOS process technology of the length of the gate in um or nm or whatever. Is there any relation between the speed of I/O and CMOS gate technology? Or in another way to ask, if I want to design 40/50 or even higher Gbps of the channel for I/O what CMOS technology should I consider to implement on as a designer?
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sheldon
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Re: relation between CMOS technology and speed of I/O
Reply #1 - Dec 14th, 2017, 6:35pm
 
Aguntuk,

 Quite often SerDes are IP that are integrated onto an SoC and the
requirements of the SoC designer/product determine the process to
be used. The process comes into play when considering the architecture,
the power, the area, ...

                                                                         Sheldon
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repah
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Re: relation between CMOS technology and speed of I/O
Reply #2 - Apr 17th, 2018, 2:41pm
 
Without design innovations, the achievable operation frequency
of circuits is around fT /10. With some design innovations
it is possible to design circuits up to fT /4 or in some cases ft/2.

See paper:

Process and device requirements for mixed-signal integrated circuits in broadband networking

This is just a guide, not a general rule.



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