Hi,
I'm trying to verify the simple AHB block by using VIPCAT, so I made simple test.v as the below

`timescale 1ps/1ps

module test2(
   HCLK,
   HRESET,
   HADDR,
   HTRANS,

...
  HLOCK,
   HGRANT
);
   parameter interface_soma = "test2.soma";
   parameter init_file   = "";
   parameter sim_control = "";
   input HCLK;
   input HRESET;
   output [31:0] HADDR;

...

     assign HBUSREQ = den_HBUSREQ;
   output HLOCK;
     reg den_HLOCK;
     assign HLOCK = den_HLOCK;
   input HGRANT;
initial
   $cdn_ahb_access(HCLK,HRESET,den_HADDR,den_HTRANS,den_HWRITE,den_HSIZE,den_HBURS
T,den_HPROT,den_HWDATA,HRDATA,HREADY,HRESP,den_HBUSREQ,den_HLOCK,HGRANT);
endmodule


And I want to use the VIPCAT to generate a BFM file for the AHB interfacing test.
But I'm stuck in the below process. How do I resolve this problem?

When I execute with the below command
$ncverilog +access+wrc test2.v


then I've got the below errors    $cdn_ahb_access(HCLK,HRESET,den_HADDR,den_HTRANS,den_HWRITE,den_HSIZE,den_HBURS
T,den_HPROT,den_HWDATA,HRDATA,HREADY,HRESP,den_HBUSREQ,den_HLOCK,HGRANT);
                 |
ncelab: *W,MISSYST (./test1.v,70|18): Unrecognized system task or function: $cdn_ahb_access (did not match built-in or user-defined names) [2.7.4(IEEE Std 1364-2001)]



Could you please help me how can I resolve this problem?.

I've attached with file (.v and executing file)
Would you help me how do I get the correct executing file?