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Settling Time Simulation of a Differential Opamp (Read 130 times)
repah
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Settling Time Simulation of a Differential Opamp
Nov 15th, 2017, 6:30pm
 
Hello,

I am using the following test bench to measure the settling time of a differential opamp ( see below )

My question is: what should the input common mode voltage be set to ?  Is this the input common mode voltage of the opamp or the common mode of the differential structure (say, 1.2V VDD - then common mode is 0.6V).

Thank you.

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settle.png
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Frank_Heart
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Re: Settling Time Simulation of a Differential Opamp
Reply #1 - Nov 16th, 2017, 11:46pm
 
It shall be the common mode of your input signals.  -Frank
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repah
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Re: Settling Time Simulation of a Differential Opamp
Reply #2 - Nov 17th, 2017, 12:14pm
 
Hello,

Thank you for your response.

The input signals of this test bench is just the step that I am applying to the opamp and the input common mode voltages.

Should I be imputing a sine wave on top of the common mode voltages for this test bench (for settling time) instead of just a step and the common mode voltage ?  I am confused on how to set this test bench up.

I have questions regarding input common mode voltages of differential opamps and associate test bench for measuring settling time in transient.

I want to design a PMOS input folded cascode fully differential opamp.  I would like the input common mode voltage to be 400mV and the output common mode voltage to be 900mV (say 0.18um CMOS technology).  

My questions are :

1) how does one design for an input common mode voltage of 400mV on the differential opamp ?  Is this basically the voltage of the combination of the Vov of the diff pair current source and the vgs of the diff pair transistor ?  Sizing and biasing them properly to achieve the 400mV input common mode voltage ?

2) how does one design for output common mode voltage of the differential opamp ?  Is this sizing the output cascode stage of the folded cascode differential opamp to achieve a swing around this common mode voltage ?

3) When I size and bias my opamp to achieve this input common mode voltage - then using the test bench I have shown the input common mode voltage is set to this value, in my case 400mv?

Thank you.
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Frank_Heart
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Re: Settling Time Simulation of a Differential Opamp
Reply #3 - Nov 17th, 2017, 10:50pm
 
Hi, Repah,

  If you want to do a CM step transient, then just short inputs and apply, 400mV <-> 500mV on the input.  

 If you want to do a differential step transient (say 200mV step), apply Vip = 400mV (CM) --> 500mV and Vin = 400mV (CM) --> 300mV.

 Regarding to how to set input/output VCM.  Usually input VCM is decided by its previous stage. You got the spec from system, and design your amplifier basing on this.  (There are also applications you need to design input common mode feedback circuit to fix your VCM, if it is used in a differential TIA. )

 Output VCM is set by your output CMFB circuit. The value is usually decided what your amplifier is going to drive, and of course you have to make sure output stage is happy working at fully tilted cases.

-Frank
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repah
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Re: Settling Time Simulation of a Differential Opamp
Reply #4 - Nov 18th, 2017, 7:57pm
 
Hello,

Thank you.

I guess what I am asking is in the figure I attached - the two "vcmi" inputs are the same - to the step and also to the opamp.  Is this correct ?  This will be the input common mode of the signal and must be within the input common mode range of the opamp.

Next, yes, I am also doing a Differential TIA.  Can you provide guidance, papers or any resources on how to design the input common mode feedback to fix VCM of a differential TIA ?

Also what do you mean by fully titled cases at the output ?  My common mode output voltage is 0.9V.  That also has to be in the output common mode range of the output of the opamp.  Is this correct ?  What do you mean again, by fully tilted cases ?

Thank you again.
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Frank_Heart
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Re: Settling Time Simulation of a Differential Opamp
Reply #5 - Nov 18th, 2017, 11:34pm
 
repah wrote on Nov 18th, 2017, 7:57pm:
Hello,

Thank you.

I guess what I am asking is in the figure I attached - the two "vcmi" inputs are the same - to the step and also to the opamp.  Is this correct ?  
-- Not necessary to be same, depending on your system. Find out who drive this amplifier and ask for the answer.

This will be the input common mode of the signal and must be within the input common mode range of the opamp.

Next, yes, I am also doing a Differential TIA.  Can you provide guidance, papers or any resources on how to design the input common mode feedback to fix VCM of a differential TIA ?
-- not in my hand, you might want to search on google

Also what do you mean by fully titled cases at the output ?
-- You have to check on system level. But you can give a differential sin signal on inputs and you should get a filtered sin signals at output. This sin signal should not crash your output stage devices

 My common mode output voltage is 0.9V.  That also has to be in the output common mode range of the output of the opamp.  Is this correct ?  What do you mean again, by fully tilted cases ?

When the output reaches their MAX swing, it is considered fully titled.


Thank you again.

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repah
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Re: Settling Time Simulation of a Differential Opamp
Reply #6 - Dec 11th, 2017, 1:07am
 
Hello,

I am having problems with this simulation - particularly with the 1T resistors.  I am using 2pf at the gate and 1pf in feedback with the opamp and am getting strange errors for the common mode voltages at the input and output of the opamp if I use 1T resistors.  If I drop them down to 100M or so, looks look fine.

Is there any reason for this ?  Is this test bench correct for a capacitive feedback differential opamp settling time calculation ?

Thank you!
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Tako
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Re: Settling Time Simulation of a Differential Opamp
Reply #7 - Jan 3rd, 2018, 1:44pm
 
Very big values of resistors (e.g. 1T) may result in some simulation problems. Isn't 100M enough for you?
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Ken Kundert
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Re: Settling Time Simulation of a Differential Opamp
Reply #8 - Jan 4th, 2018, 11:02am
 
1TΩ resistors? Those are at the input right? Your schematic is hard to read.

Those appear to be there for common mode biasing? Why don't you connect them to the common mode bias voltage. That way your amplifier will bias up correctly regardless of the DC voltage of your inputs.

If you want to know about how to resolve the errors from the 1TΩ resistors, perhaps you should tell us what the error is.

-Ken
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repah
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Re: Settling Time Simulation of a Differential Opamp
Reply #9 - Jan 4th, 2018, 3:10pm
 
Hello,

Thank you for your responses.

Mr. Kundert, as Tako mentioned, the "error" I am seeing is the common mode voltage not settling to the correct value, that I am expecting.  I am expecting the opamp to settle to it's input common mode value after the the switched capacitor common mode feedback settles.

I am using the 1T resistors to set the input common mode of the amplifier.

As I mentioned when I use 100 M resistors I find it settles to the input common mode voltage I expect, but when I use 1 T resistors it settles to a higher value than I expect.

This is what I am experiencing.

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Tako
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Re: Settling Time Simulation of a Differential Opamp
Reply #10 - Jan 5th, 2018, 1:45am
 
You may also want to change the number of iterations for the convergence algorithm. More steps require more time, but finally you should be able to achieve desired voltage.

You may also do a trick and use .ic (initial conditions) directive.
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Ken Kundert
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Re: Settling Time Simulation of a Differential Opamp
Reply #11 - Jan 5th, 2018, 9:42am
 
If the common mode voltage does not settle to the desired value with 1TΩ resistors, but does with 100MΩ resistors, it suggests that there is current flowing through those resistors. Any chance you amplifier exhibits an input bias current?

-Ken
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