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Trade off on using SC DAC inside CT sigma-delta ADC (Read 44 times)
neoflash
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Trade off on using SC DAC inside CT sigma-delta ADC
Nov 14th, 2017, 4:49pm
 
There is a technique that people use to reduce jitter sensitivity in CT sigma delta ADC.

As shown in the figure, a SC DAC used for feedback.

What is the price paid for choosing this approach?

One issue I can think of is, the instantaneous kick of SC circuit to the integrator might be a problem limiting linearity.

Any comments?

Neo
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SC_CT_ADC.png
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Frank_Heart
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Re: Trade off on using SC DAC inside CT sigma-delta ADC
Reply #1 - Nov 17th, 2017, 12:17am
 
Hi, Neo,

 I would suggest you to read the book :

 Understanding Delta-Sigma Data Converters, 2nd Edition

 http://www.wiley.com/WileyCDA/WileyTitle/productCd-1119258278.html

 They have detailed discussions on SC-DAC (page 328), and explain why it is not popular.

  "In summary, while the SC feedback DAC is an intuitively appealing idea for combating clock jitter, it presents many practical implementation challenges. For one, the linearity needed of the first integrator is greatly increased due to the high peak-to-average ratio of the feedback waveform. Next, the inherent anti-aliasing feature, the hallmark of continuous-time SD modulation, is limited to about 20dB".

  BTW, if anyone have an intuitive way to understand "the inherent anti-aliasing feature, the hallmark of continuous-time SD modulation, is limited to about 20dB" in SC-DAC SDM, please share.

-Frank
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