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VerilogA model demo for continous-time sigma delta data converters (Read 53 times)
neoflash
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VerilogA model demo for continous-time sigma delta data converters
Nov 13th, 2017, 12:33pm
 
I did search in google and found a bunch of short papers in this area. However, it could be much more handy if we can get a few example cases that we can play with and expand.

Would appreciate if anyone have done this search before and could post a few links for sharing.

Regards,
Neo
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polyam
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Re: VerilogA model demo for continous-time sigma delta data converters
Reply #1 - Nov 20th, 2017, 8:52pm
 
Hi neoflash,

I am afraid that you cannot find such things! I would suggest building one by yourself.
Just start with two ideal op-amps, a comparator and a bunch of resistors and capacitor you can easily implement an ideal DSM.
You can practice with a topology like this:

http://www.mdpi.com/2079-9268/2/3/197/htm

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