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Extract parameters for custom Verilog-A models (Read 699 times)
georgtree
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Extract parameters for custom Verilog-A models
Nov 04th, 2017, 12:47pm
 
Hello everyone!
I faced with folowing problem: how can I extract parameters for my Verilog-A model ?
All common models like BSIM, EKV, HiSIM and etc have default implementaions in programs like IC-CAP, MBP, UTMOS. But how can I use such tools for my handwritten models? Does anyone have such experience?
Thank you for help!
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georgtree
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Re: Extract parameters for custom Verilog-A models
Reply #1 - Dec 10th, 2017, 4:05am
 
Does anybody know?(
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