Hello everyone here,

I have tested the rail to rail buffer (constant gm topology:65nm) in the lab. I have tested 3 samples (chip1, chip2, chip 3 in fig below) and plotted the input out char with simulation results also.
I am not able to understand why at one of the rail (either zero or 1.2 ) the output of the r2r is showing pretty much deviation from the simulation (see first comment where I put the other figure )?
Can someone explain this behaviour? If anyone needs more information to explain the behaviour kindly let me know.

Hi, kabir,

 There is always gain drop when Vout approaches to rail, completely driving PMOS (or NMOS) side to triode region, such that the systematic offset gains up, if your feedback loop still holds and nothing is broken (working in triode region) in previous gain stages.  

 Say you have 3-stage amplifier, the 1st & 2nd stage gain is already high enough to bring systematic offset below 1mV. But remember you are going to have mis-match in real circuit, which could drive the 1st & 2nd stage broken in this case. So your overall offset will be much larger. This might be the reason, you get much higher offset than your schematic results.  You should run some MC to check the offset @ fully titled cases.

Regards,
Frank