Hi,

I am trying to use the ADC Verilog-A model given in the

**"Designer's Guide of Verilog AMS"** book (

**Ch. 3, Listing 26**). The code is -

**Code:**// N-bit Analog to Digital Converter
`include "disciplines.vams"
`include "constants.h"
module ideal_adc (out, in, clk);
parameter integer bits = 8 from [1:24]; // resolution (bits)
parameter real fullscale = 1.0; // input range is from 0 to fullscale (V)
parameter real td = 0; // delay from clock edge to output (s)
parameter real tt = 0; // transition time of output (s)
parameter real vdd = 5.0; // voltage level of logic 1 (V)
parameter real thresh = vdd/2; // logic threshold level (V)
parameter integer dir = 1 from [–1:1] exclude 0; // 1 for rising edges, –1 for falling
input in, clk;
output [0:bits–1] out;
voltage in, clk;
voltage [0:bits–1] out;
real sample, midpoint;
integer result[0:bits–1];
genvar i;
analog begin
@(cross(V(clk)–thresh, +1) or initial_step) begin
sample = V(in);
midpoint = fullscale/2.0;
for (i = bits – 1; i >= 0; i = i – 1 ) begin
if (sample > midpoint) begin
result[i] = vdd;
sample = sample – midpoint;
end else begin
result[i] = 0.0;
end
sample = 2.0*sample;
end
end
for (i = 0; i < bits; i = i + 1) begin
V(out[i]) <+ transition(result[i], td, tt);
end
end
endmodule

In this the output port has variable width defined by the integer variable "bits".

The problem that I am facing is - when I am trying to create the symbol (Cadence Virtuoso 6.1.6), it is taking the output port name as

**out<0:-1>**. Changing it to

**out** is not accepted. However, if I set

**bits = 8**, and hard-code the port declaration as -

**Code:**output [0:7] out;
voltage [0:7] out;

then there is no issue - the port name is taken as

**out<0:7>**.

Can somebody, please help me out in fixing this problem (how to properly set the output port name even after keeping port word-length variable through the parameter

**bits**.