The Designer's Guide Community
Forum
ForumVerilog-AMSAnalysisModelingDesignTheory
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
Apr 19th, 2024, 7:05am
 
  HomeHelpSearchLoginRegisterPM to admin    
The Designer's Guide Community Forum › Analog Verification › Analog Functional Verification › Assertions inside Connect Modules
‹ Previous topic | Next topic ›
Pages: 1
Send Topic Print
Assertions inside Connect Modules (Read 83 times)
sgh2050
New Member
*
Offline



Posts: 2
Assertions inside Connect Modules
Sep 18th, 2017, 8:03am  
Hi All,

I am new to AMS verification. I have following question.

Please let me know if I can place assertions inside connect module for E2L. The purpose is to check that Signals coming from analog to digital are at 1.2 V level. This is to check that there are Level shifters in analog so that 3.3v is correctly converted to 1.2V before going to digital

We use Cadence. How can i tell cadence irun to pick a  a custom E2L connect module

Best Regards
Back to top
 
 
View Profile   IP Logged
nischaybm
New Member
*
Offline



Posts: 2
Re: Assertions inside Connect Modules
Reply #1 - Nov 30th, 2017, 1:12am  
Hi sgh2050,

I am not sure if you can add assertions, that may need you to have a clk signal.

default connect module doesn't complain if the signal Voltage is higher than expected.
you can right your own connect modules for this purpose, you can include them like them in ADE,

ADE--> SETUP --> connect Rules

Thanks,
Back to top
 
 
View Profile   IP Logged
Pages: 1
Send Topic Print
‹ Previous topic | Next topic ›
« Home ‹ Board
The Designer's Guide Community Forum » Powered by YaBB 2.2.2!
YaBB © 2000-2008. All Rights Reserved.
Copyright 2002-2024 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.