Unfortunately, I will not be able to provide you a cookbook recipe how to design a PLL .... but cycle jitter you can simulate either using:

1.) pnoise analysis (will only work for the sub-blocks like VCO and not the entire PLL)

2.) transient noise and period_jitter function in calculator. Even though transient noise simulation of the full PLL might be challenging (combination of high frequency in VCO but low frequency time constants in loop)

I would suggest you to read some papers about PLL with similar specs you are aiming for.

Period jitter is the difference between the actual period and the ideal reference period.
Cycle to cycle jitter is the difference between period i+1 and period i.

Cycle to cycle jitter is more suitable for measurements than period or edge jitter as you don't need a reference (the reference is the previous period). However, you should keep in mind that for low frequency jitter, the clock edges might be correlated. This low frequency jitter is then not considered in period or cycle-to-cycle jitter.
TIE (time interval error) jitter is also often used, as it can conveniently be measured with a scope.

I guess it depends on your system which kind of jitter is of interest.