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Uses of Macro in Verilog-AMS (Read 209 times)
Gp
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Uses of Macro in Verilog-AMS
Aug 30th, 2017, 4:48am
 
Hi,

I want to use following Verilog-ams macro for range check in cadence environment:

`RANGE_CHECK(expr,"NAME", max,min,ef,en)

For detailed reference, use following link:

https://books.google.co.in/books?id=RKrfAwAAQBAJ&pg=PA92&lpg=PA92&dq=%60AVDD+che...
ck+in+mixed+signal+methodology+guide&source=bl&ots=uXomWUVSRy&sig=s37V_5RGMGbK0q
wNuanhB1qqpJo&hl=en&sa=X&ved=0ahUKEwjq2PH27_7VAhWKhVQKHUS5CXkQ6AEINjAD#v=onepage
&q=%60AVDD%20check%20in%20mixed%20signal%20methodology%20guide&f=false



So, How to use this type of macro in Verilog-ams?
When I use, error through about "this type of macro doesn't support".
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Andrew Beckett
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Re: Uses of Macro in Verilog-AMS
Reply #1 - Sep 9th, 2017, 12:07am
 
You'd have to define the macro - these are not standard built-in macros. Did you do that? The book only gives a snippet and doesn't include the definition (I don't have the actual book to hand as it's in my office, but the wording of the excerpt on the link you gave doesn't seem to show the definition).

Andrew.
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Gp
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Re: Uses of Macro in Verilog-AMS
Reply #2 - Sep 11th, 2017, 1:26am
 
I didn't try with defined macro. And I have not idea about Verilog-AMS macro.
Do you have any reference example of Verilog-AMS macro?
If yes, please help me.
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