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Ground plane in silicon cmos rf design (Read 880 times)
engrvip
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Ground plane in silicon cmos rf design
Aug 22nd, 2017, 6:22pm
 
Hi

I am designing 1.1GHz lna in silicon cmos technology. Is ground plane required for design at this frequency. If yes, should this ground plane be accessed from package plane using TSV (  through silicon via) or one of lower metal layers in stack can be used for this purpose.

Regards
Engrvip
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